From: Florent Kermarrec Date: Wed, 12 Dec 2018 08:38:10 +0000 (+0100) Subject: soc/cores/cpu/lm32: add submodule/rtl to include path (needed for lm32_include.v) X-Git-Tag: 24jan2021_ls180~1443 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6d6c2b4c4562ebc68dc0ded11759be39116a454c;p=litex.git soc/cores/cpu/lm32: add submodule/rtl to include path (needed for lm32_include.v) --- diff --git a/litex/soc/cores/cpu/lm32/core.py b/litex/soc/cores/cpu/lm32/core.py index d32d7ba6..b79a7fd6 100644 --- a/litex/soc/cores/cpu/lm32/core.py +++ b/litex/soc/cores/cpu/lm32/core.py @@ -88,6 +88,7 @@ class LM32(Module): "lm32_debug.v", "lm32_itlb.v", "lm32_dtlb.v") + platform.add_verilog_include_path(os.path.join(vdir, "submodule", "rtl")) if variant == "minimal": platform.add_verilog_include_path(os.path.join(vdir, "config_minimal")) elif variant == "lite":