From: Luke Kenneth Casson Leighton Date: Mon, 31 Aug 2020 11:06:24 +0000 (+0100) Subject: add XER to fastregs and "construct" it in mfspr/mtspr X-Git-Tag: semi_working_ecp5~219 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6d7d558cda742f3f095f65cfee7255f5f5f70bfd;p=soc.git add XER to fastregs and "construct" it in mfspr/mtspr --- diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py index 1bdcd3ff..4405cf2c 100644 --- a/src/soc/decoder/power_decoder2.py +++ b/src/soc/decoder/power_decoder2.py @@ -147,6 +147,8 @@ class DecodeA(Elaboratable): comb += self.fast_out.data.eq(FastRegs.SRR1) comb += self.fast_out.ok.eq(1) with m.Case(SPR.XER.value): + comb += self.fast_out.data.eq(FastRegs.XER) + comb += self.fast_out.ok.eq(1) pass # do nothing # : map to internal SPR numbers # XXX TODO: dec and tb not to go through mapping. @@ -328,6 +330,8 @@ class DecodeOut(Elaboratable): comb += self.fast_out.data.eq(FastRegs.SRR1) comb += self.fast_out.ok.eq(1) with m.Case(SPR.XER.value): + comb += self.fast_out.data.eq(FastRegs.XER) + comb += self.fast_out.ok.eq(1) pass # do nothing # : map to internal SPR numbers # XXX TODO: dec and tb not to go through mapping. diff --git a/src/soc/fu/spr/main_stage.py b/src/soc/fu/spr/main_stage.py index f4261b62..de1ab2f2 100644 --- a/src/soc/fu/spr/main_stage.py +++ b/src/soc/fu/spr/main_stage.py @@ -48,22 +48,23 @@ class SPRMainStage(PipeModBase): with m.Case(MicrOp.OP_MTSPR): with m.Switch(spr): # fast SPRs first - with m.Case(SPR.CTR, SPR.LR, SPR.TAR, SPR.SRR0, SPR.SRR1): + with m.Case(SPR.CTR, SPR.LR, SPR.TAR, SPR.SRR0, + SPR.SRR1, SPR.XER): comb += fast1_o.data.eq(a_i) comb += fast1_o.ok.eq(1) - # XER is constructed - with m.Case(SPR.XER): - # sticky - comb += so_o.data.eq(a_i[63-XER_bits['SO']]) - comb += so_o.ok.eq(1) - # overflow - comb += ov_o.data[0].eq(a_i[63-XER_bits['OV']]) - comb += ov_o.data[1].eq(a_i[63-XER_bits['OV32']]) - comb += ov_o.ok.eq(1) - # carry - comb += ca_o.data[0].eq(a_i[63-XER_bits['CA']]) - comb += ca_o.data[1].eq(a_i[63-XER_bits['CA32']]) - comb += ca_o.ok.eq(1) + # XER is constructed + with m.If(spr == SPR.XER): + # sticky + comb += so_o.data.eq(a_i[63-XER_bits['SO']]) + comb += so_o.ok.eq(1) + # overflow + comb += ov_o.data[0].eq(a_i[63-XER_bits['OV']]) + comb += ov_o.data[1].eq(a_i[63-XER_bits['OV32']]) + comb += ov_o.ok.eq(1) + # carry + comb += ca_o.data[0].eq(a_i[63-XER_bits['CA']]) + comb += ca_o.data[1].eq(a_i[63-XER_bits['CA32']]) + comb += ca_o.ok.eq(1) # slow SPRs TODO # move from SPRs @@ -71,18 +72,22 @@ class SPRMainStage(PipeModBase): comb += o.ok.eq(1) with m.Switch(spr): # fast SPRs first - with m.Case(SPR.CTR, SPR.LR, SPR.TAR, SPR.SRR0, SPR.SRR1): + with m.Case(SPR.CTR, SPR.LR, SPR.TAR, SPR.SRR0, SPR.SRR1, + SPR.XER): comb += o.data.eq(fast1_i) - # XER is constructed - with m.Case(SPR.XER): - # sticky - comb += o[63-XER_bits['SO']].eq(so_i) - # overflow - comb += o[63-XER_bits['OV']].eq(ov_i[0]) - comb += o[63-XER_bits['OV32']].eq(ov_i[1]) - # carry - comb += o[63-XER_bits['CA']].eq(ca_i[0]) - comb += o[63-XER_bits['CA32']].eq(ca_i[1]) + with m.If(spr == SPR.XER): + # bits 0:31 and 35:43 are treated as reserved + # and return 0s when read using mfxer + comb += o[32:64].eq(0) # MBS0 bits 0-31 + comb += o[63-43:64-35].eq(0) # MSB0 bits 35-43 + # sticky + comb += o[63-XER_bits['SO']].eq(so_i) + # overflow + comb += o[63-XER_bits['OV']].eq(ov_i[0]) + comb += o[63-XER_bits['OV32']].eq(ov_i[1]) + # carry + comb += o[63-XER_bits['CA']].eq(ca_i[0]) + comb += o[63-XER_bits['CA32']].eq(ca_i[1]) # slow SPRs TODO comb += self.o.ctx.eq(self.i.ctx) diff --git a/src/soc/litex/florent/sim.py b/src/soc/litex/florent/sim.py index d3c79017..4fee28f4 100755 --- a/src/soc/litex/florent/sim.py +++ b/src/soc/litex/florent/sim.py @@ -308,7 +308,7 @@ class LibreSoCSim(SoCSDRAM): ) if cpu == "libresoc": - self.comb += active_dbg_cr.eq((0x10300 <= pc) & (pc <= 0x10e00)) + self.comb += active_dbg_cr.eq((0x10300 <= pc) & (pc <= 0x11700)) #self.comb += active_dbg_cr.eq(1) # get the CR diff --git a/src/soc/regfile/regfiles.py b/src/soc/regfile/regfiles.py index 505fb587..0dce110e 100644 --- a/src/soc/regfile/regfiles.py +++ b/src/soc/regfile/regfiles.py @@ -79,9 +79,9 @@ class IntRegs(RegFileMem): #class IntRegs(RegFileArray): class FastRegs(RegFileMem): #RegFileArray): """FastRegs - FAST regfile - CTR, LR, TAR, SRR1, SRR2 + FAST regfile - CTR, LR, TAR, SRR1, SRR2, XER - * QTY 5of 64-bit registers + * QTY 6of 64-bit registers * 2R1W * Array-based unary-indexed (not binary-indexed) * write-through capability (read on same cycle as write) @@ -91,8 +91,9 @@ class FastRegs(RegFileMem): #RegFileArray): TAR = 2 SRR0 = 3 SRR1 = 4 + XER = 5 # non-XER bits def __init__(self): - super().__init__(64, 5) + super().__init__(64, 6) self.w_ports = {'fast1': self.write_port("dest1"), } self.r_ports = {'fast1': self.read_port("src1"),