From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 12 Jul 2018 02:07:56 +0000 (+0100)
Subject: add slids
X-Git-Tag: convert-csv-opcode-to-binary~5061
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6d826d32103df9c502bc4a561d47677b1333d76d;p=libreriscv.git

add slids
---

diff --git a/shakti/m_class/libre_riscv_chennai_2018.tex b/shakti/m_class/libre_riscv_chennai_2018.tex
index 536afd6e3..e218acd5c 100644
--- a/shakti/m_class/libre_riscv_chennai_2018.tex
+++ b/shakti/m_class/libre_riscv_chennai_2018.tex
@@ -273,7 +273,7 @@
   \end{itemize}
    {\it Jacob Bachmeyer's Cache-control proposal turns L1 Cache into
    scratchpad RAM.  RVV is just too heavy (sorry!), Simple-V much
-   more light-weight and flexible.
+   more light-weight and flexible ($O(1)$ ISA proliferation)
    }
 }
 
@@ -289,7 +289,20 @@
 \frame{\frametitle{Summary}
 
  \begin{itemize}
-   \item TODO
+   \item Making a commercially-desirable SoC is neither academically
+         nor standard-investor sexy!  No AI. Boring. zzzz
+   \item Luckily there is an anonymous sponsor who needs an SoC that
+	     doesn't exist (who knows the commercial benefits of Libre)
+   \item Shakti Group know the benefits (cost, sovereignty) of a Libre
+         Mobile-Class SoC as well (No spying on India citizens!)
+   \item A Libre GPU, even a modest performer (100T/s etc.) 
+	     is the biggest technical risk / unknown (besides DDR3/4).\\
+	     (fall-back is GC800. Do please help with a Libre GPU!)
+    \item DDR3/4 and eMMC are the main high-risk interfaces\\
+	     (there are fall-back strategies in place)
+	\item Ultimately the strategy is all about cost reduction
+	      vs risk mitigation,
+	      with Libre/Ethical prioritised over "convenience"
   \end{itemize}
 }