From: lkcl <lkcl@web>
Date: Sun, 5 Sep 2021 16:32:16 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~215
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6d82bd8ebae258d686ca289ba76d07a5e7ab995c;p=libreriscv.git

---

diff --git a/openpower/sv/ldst.mdwn b/openpower/sv/ldst.mdwn
index 40b5793dd..3a251bf3e 100644
--- a/openpower/sv/ldst.mdwn
+++ b/openpower/sv/ldst.mdwn
@@ -47,12 +47,6 @@ a number of different modes:
 Also included in SVP64 LD/ST is both signed and unsigned Saturation,
 as well as Eement-width overrides and Twin-Predication.
 
-*Missing* from Scalar Power ISA v3.0B is a scalar [[mv.x]] instruction
-on top of which any good Vector ISA provides Vector Scatter-Gather.
-Due to the way that SVP64 is desigbed, this needs to be added separately
-(to Scalar Power ISA) before the
-Vectorised variant can also be made available.
-
 # Vectorisation of Scalar Power ISA v3.0B
 
 OpenPOWER Load/Store operations may be seen from [[isa/fixedload]] and