From: Luke Kenneth Casson Leighton Date: Wed, 23 Jun 2021 21:42:37 +0000 (+0100) Subject: only add SVP64 bitreverse mode for LDs at the moment. ST would need 4 operands X-Git-Tag: xlen-bcd~402 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6d86b3df2af9ca2d1acdac155973d3582210d06d;p=openpower-isa.git only add SVP64 bitreverse mode for LDs at the moment. ST would need 4 operands add RC to PowerDecoder add create_decode_svp64 sort out Forms and Const names in enums --- diff --git a/openpower/isatables/fields.text b/openpower/isatables/fields.text index 42a02303..d939625a 100644 --- a/openpower/isatables/fields.text +++ b/openpower/isatables/fields.text @@ -642,7 +642,7 @@ RC (21:25) Field used to specify a GPR to be used as a source. - Formats: VA + Formats: VA, SVD, SVDS Rc (31) RECORD bit. 0 Do not alter the Condition Register. diff --git a/openpower/isatables/svldst_major.csv b/openpower/isatables/svldst_major.csv new file mode 100644 index 00000000..2c4a8456 --- /dev/null +++ b/openpower/isatables/svldst_major.csv @@ -0,0 +1,13 @@ +opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry out,ldst len,BR,sgn ext,upd,rsrv,32b,sgn,rc,lk,sgl pipe,comment,form +34,LDST,OP_LOAD,RA_OR_ZERO,CONST_SVD,RC,RT,NONE,NONE,0,0,ZERO,0,is1B,0,0,0,0,0,0,NONE,0,1,lbz,SVD +35,LDST,OP_LOAD,RA_OR_ZERO,CONST_SVD,RC,RT,NONE,NONE,0,0,ZERO,0,is1B,0,0,1,0,0,0,NONE,0,1,lbzu,SVD +50,LDST,OP_LOAD,RA_OR_ZERO,CONST_SVD,RC,FRT,NONE,NONE,0,0,ZERO,0,is8B,0,0,0,0,0,0,NONE,0,1,lfd,SVD +51,LDST,OP_LOAD,RA,CONST_SVD,RC,FRT,NONE,NONE,0,0,ZERO,0,is8B,0,0,1,0,0,0,NONE,0,1,lfdu,SVD +48,LDST,OP_LOAD,RA_OR_ZERO,CONST_SVD,RC,FRT,NONE,NONE,0,0,ZERO,0,is4B,0,0,0,0,1,0,NONE,0,1,lfs,SVD +49,LDST,OP_LOAD,RA,CONST_SVD,RC,FRT,NONE,NONE,0,0,ZERO,0,is4B,0,0,1,0,1,0,NONE,0,1,lfsu,SVD +42,LDST,OP_LOAD,RA_OR_ZERO,CONST_SVD,RC,RT,NONE,NONE,0,0,ZERO,0,is2B,0,1,0,0,0,0,NONE,0,1,lha,SVD +43,LDST,OP_LOAD,RA_OR_ZERO,CONST_SVD,RC,RT,NONE,NONE,0,0,ZERO,0,is2B,0,1,1,0,0,0,NONE,0,1,lhau,SVD +40,LDST,OP_LOAD,RA_OR_ZERO,CONST_SVD,RC,RT,NONE,NONE,0,0,ZERO,0,is2B,0,0,0,0,0,0,NONE,0,1,lhz,SVD +41,LDST,OP_LOAD,RA_OR_ZERO,CONST_SVD,RC,RT,NONE,NONE,0,0,ZERO,0,is2B,0,0,1,0,0,0,NONE,0,1,lhzu,SVD +32,LDST,OP_LOAD,RA_OR_ZERO,CONST_SVD,RC,RT,NONE,NONE,0,0,ZERO,0,is4B,0,0,0,0,0,0,NONE,0,1,lwz,SVD +33,LDST,OP_LOAD,RA_OR_ZERO,CONST_SVD,RC,RT,NONE,NONE,0,0,ZERO,0,is4B,0,0,1,0,0,0,NONE,0,1,lwzu,SVD diff --git a/openpower/isatables/svldstmajor.csv b/openpower/isatables/svldstmajor.csv deleted file mode 100644 index 1c300126..00000000 --- a/openpower/isatables/svldstmajor.csv +++ /dev/null @@ -1,23 +0,0 @@ -opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry out,ldst len,BR,sgn ext,upd,rsrv,32b,sgn,rc,lk,sgl pipe,comment,form -34,LDST,OP_LOAD,RA_OR_ZERO,CONST_SSI,RC,RT,NONE,NONE,0,0,ZERO,0,is1B,0,0,0,0,0,0,NONE,0,1,lbz,SVD -35,LDST,OP_LOAD,RA_OR_ZERO,CONST_SSI,RC,RT,NONE,NONE,0,0,ZERO,0,is1B,0,0,1,0,0,0,NONE,0,1,lbzu,SVD -50,LDST,OP_LOAD,RA_OR_ZERO,CONST_SSI,RC,FRT,NONE,NONE,0,0,ZERO,0,is8B,0,0,0,0,0,0,NONE,0,1,lfd,SVD -51,LDST,OP_LOAD,RA,CONST_SSI,RC,FRT,NONE,NONE,0,0,ZERO,0,is8B,0,0,1,0,0,0,NONE,0,1,lfdu,SVD -48,LDST,OP_LOAD,RA_OR_ZERO,CONST_SSI,RC,FRT,NONE,NONE,0,0,ZERO,0,is4B,0,0,0,0,1,0,NONE,0,1,lfs,SVD -49,LDST,OP_LOAD,RA,CONST_SSI,RC,FRT,NONE,NONE,0,0,ZERO,0,is4B,0,0,1,0,1,0,NONE,0,1,lfsu,SVD -42,LDST,OP_LOAD,RA_OR_ZERO,CONST_SSI,RC,RT,NONE,NONE,0,0,ZERO,0,is2B,0,1,0,0,0,0,NONE,0,1,lha,SVD -43,LDST,OP_LOAD,RA_OR_ZERO,CONST_SSI,RC,RT,NONE,NONE,0,0,ZERO,0,is2B,0,1,1,0,0,0,NONE,0,1,lhau,SVD -40,LDST,OP_LOAD,RA_OR_ZERO,CONST_SSI,RC,RT,NONE,NONE,0,0,ZERO,0,is2B,0,0,0,0,0,0,NONE,0,1,lhz,SVD -41,LDST,OP_LOAD,RA_OR_ZERO,CONST_SSI,RC,RT,NONE,NONE,0,0,ZERO,0,is2B,0,0,1,0,0,0,NONE,0,1,lhzu,SVD -32,LDST,OP_LOAD,RA_OR_ZERO,CONST_SSI,RC,RT,NONE,NONE,0,0,ZERO,0,is4B,0,0,0,0,0,0,NONE,0,1,lwz,SVD -33,LDST,OP_LOAD,RA_OR_ZERO,CONST_SSI,RC,RT,NONE,NONE,0,0,ZERO,0,is4B,0,0,1,0,0,0,NONE,0,1,lwzu,SVD -38,LDST,OP_STORE,RA_OR_ZERO,CONST_SSI,RS,RC,NONE,NONE,0,0,ZERO,0,is1B,0,0,0,0,0,0,NONE,0,1,stb,SVD -39,LDST,OP_STORE,RA_OR_ZERO,CONST_SSI,RS,RC,NONE,NONE,0,0,ZERO,0,is1B,0,0,1,0,0,0,NONE,0,1,stbu,SVD -54,LDST,OP_STORE,RA_OR_ZERO,CONST_SSI,FRS,RC,NONE,NONE,0,0,ZERO,0,is8B,0,0,0,0,0,0,NONE,0,1,stfd,SVD -55,LDST,OP_STORE,RA,CONST_SSI,FRS,RC,NONE,NONE,0,0,ZERO,0,is8B,0,0,1,0,0,0,NONE,0,1,stfdu,SVD -52,LDST,OP_STORE,RA_OR_ZERO,CONST_SSI,FRS,RC,NONE,NONE,0,0,ZERO,0,is4B,0,0,0,0,1,0,NONE,0,1,stfs,SVD -53,LDST,OP_STORE,RA,CONST_SSI,FRS,RC,NONE,NONE,0,0,ZERO,0,is4B,0,0,1,0,1,0,NONE,0,1,stfsu,SVD -44,LDST,OP_STORE,RA_OR_ZERO,CONST_SSI,RS,RC,NONE,NONE,0,0,ZERO,0,is2B,0,0,0,0,0,0,NONE,0,1,sth,SVD -45,LDST,OP_STORE,RA_OR_ZERO,CONST_SSI,RS,RC,NONE,NONE,0,0,ZERO,0,is2B,0,0,1,0,0,0,NONE,0,1,sthu,SVD -36,LDST,OP_STORE,RA_OR_ZERO,CONST_SSI,RS,RC,NONE,NONE,0,0,ZERO,0,is4B,0,0,0,0,0,0,NONE,0,1,stw,SVD -37,LDST,OP_STORE,RA_OR_ZERO,CONST_SSI,RS,RC,NONE,NONE,0,0,ZERO,0,is4B,0,0,1,0,0,0,NONE,0,1,stwu,SVD diff --git a/src/openpower/decoder/power_decoder.py b/src/openpower/decoder/power_decoder.py index d53c0676..c06cb76f 100644 --- a/src/openpower/decoder/power_decoder.py +++ b/src/openpower/decoder/power_decoder.py @@ -228,7 +228,7 @@ class PowerOp: if field not in power_op_csvmap: continue csvname = power_op_csvmap[field] - #print(field, ptype, csvname, row) + # log(field, ptype, csvname, row) val = row[csvname] if csvname == 'upd' and isinstance(val, int): # LDSTMode different val = ptype(val) @@ -540,6 +540,54 @@ class TopPowerDecoder(PowerDecoder): return [self.raw_opcode_in, self.bigendian] + PowerDecoder.ports(self) +############################################################# +# PRIMARY FUNCTION SPECIFYING ALTERNATIVE SVP64 POWER DECODER + +def create_pdecode_svp64(name=None, col_subset=None, row_subset=None, + include_fp=False): + """create_pdecode - creates a cascading hierarchical POWER ISA decoder + + subsetting of the PowerOp decoding is possible by setting col_subset + """ + log ("create_pdecode_svp64", name, col_subset, row_subset, include_fp) + + # some alteration to the CSV files is required for SV so we use + # a class to do it + isa = SVP64RM() + get_csv = isa.get_svp64_csv + + # minor opcodes. + pminor = [ + Subdecoder(pattern=58, opcodes=get_csv("svldst_minor_58.csv"), + opint=True, bitsel=(0, 2), suffix=None, subdecoders=[]), + # nope - needs 4-in regs + #Subdecoder(pattern=62, opcodes=get_csv("svldst_minor_62.csv"), + # opint=True, bitsel=(0, 2), suffix=None, subdecoders=[]), + ] + + # FP 63L/H decoders. TODO: move mffsfamily to separate subdecoder + if False and include_fp: + pminor.append( + Subdecoder(pattern=63, opcodes=get_csv("minor_63.csv"), + opint=False, bitsel=(1, 11), suffix=None, + subdecoders=[]), + ) + pminor.append( + Subdecoder(pattern=59, opcodes=get_csv("minor_59.csv"), + opint=False, bitsel=(1, 11), suffix=None, + subdecoders=[]), + ) + + # top level: extra merged with major + dec = [] + opcodes = get_csv("svldst_major.csv") + dec.append(Subdecoder(pattern=None, opint=True, opcodes=opcodes, + bitsel=(26, 32), suffix=None, subdecoders=pminor)) + + return TopPowerDecoder(32, dec, name=name, col_subset=col_subset, + row_subset=row_subset) + + #################################################### # PRIMARY FUNCTION SPECIFYING THE FULL POWER DECODER @@ -634,8 +682,13 @@ if __name__ == '__main__': f.write(vl) # full decoder - pdecode = create_pdecode(include_fp=True) vl = rtlil.convert(pdecode, ports=pdecode.ports()) with open("decoder.il", "w") as f: f.write(vl) + + # full SVP64 decoder + pdecode = create_pdecode_svp64(include_fp=True) + vl = rtlil.convert(pdecode, ports=pdecode.ports()) + with open("decoder_svp64.il", "w") as f: + f.write(vl) diff --git a/src/openpower/decoder/power_decoder2.py b/src/openpower/decoder/power_decoder2.py index 2cb25a24..b9f121a2 100644 --- a/src/openpower/decoder/power_decoder2.py +++ b/src/openpower/decoder/power_decoder2.py @@ -354,6 +354,9 @@ class DecodeC(Elaboratable): with m.Case(In3Sel.RS): comb += reg.data.eq(self.dec.RS) comb += reg.ok.eq(1) + with m.Case(In3Sel.RC): + comb += reg.data.eq(self.dec.RC) + comb += reg.ok.eq(1) return m diff --git a/src/openpower/decoder/power_enums.py b/src/openpower/decoder/power_enums.py index 987be310..3ed52737 100644 --- a/src/openpower/decoder/power_enums.py +++ b/src/openpower/decoder/power_enums.py @@ -116,6 +116,8 @@ class Form(Enum): Z22 = 27 Z23 = 28 SVL = 29 # Simple-V for setvl instruction + SVD = 30 # Simple-V for LD/ST bit-reverse, variant of D-Form + SVDS = 31 # Simple-V for LD/ST bit-reverse, variant of DS-Form # Simple-V svp64 fields https://libre-soc.org/openpower/sv/svp64/ @@ -403,8 +405,8 @@ class In2Sel(Enum): SPR = 12 RS = 13 # for shiftrot (M-Form) FRB = 14 - CONST_SSI = 15 # for SVD-Form - CONST_SDS = 16 # for SVDS-Form + CONST_SVD = 15 # for SVD-Form + CONST_SVDS = 16 # for SVDS-Form @unique @@ -414,6 +416,7 @@ class In3Sel(Enum): RB = 2 # for shiftrot (M-Form) FRS = 3 FRC = 4 + RC = 5 # for SVP64 bit-reverse LD/ST @unique diff --git a/src/openpower/decoder/power_fields.py b/src/openpower/decoder/power_fields.py index 450e1cfa..8c972625 100644 --- a/src/openpower/decoder/power_fields.py +++ b/src/openpower/decoder/power_fields.py @@ -146,6 +146,7 @@ class DecodeFields: "RT": self.FormX.RT, "RA": self.FormX.RA, "RB": self.FormX.RB, + "RC": self.FormVA.RB, "SI": self.FormD.SI, "UI": self.FormD.UI, "L": self.FormD.L,