From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 15 Feb 2022 15:43:30 +0000 (+0000)
Subject: attempt to do 8-bit downconvert on wishbone bus for uart,
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6d88cc5ca3b72929942a6cc3194521ae36b9eaaa;p=ls2.git

attempt to do 8-bit downconvert on wishbone bus for uart,
but it is probably actually 8-bit data aligned to 32-bit
(see soc.vhdl in microwatt)
also set CTS,DSR,RI, DCD to default values
---

diff --git a/src/ls2.py b/src/ls2.py
index df3fb59..a7b5614 100644
--- a/src/ls2.py
+++ b/src/ls2.py
@@ -48,7 +48,7 @@ class DDR3SoC(SoC, Elaboratable):
                  ddrphy_addr, dramcore_addr,
                  ddr_addr, fw_addr=0x0000_0000,
                  firmware=None,
-                 clk_freq=40e6):
+                 clk_freq=50e6):
 
         # set up wishbone bus arbiter and decoder. arbiter routes,
         # decoder maps local-relative addressed satellites to global addresses
@@ -100,13 +100,22 @@ class DDR3SoC(SoC, Elaboratable):
         self.ram = SRAMPeripheral(size=4096)
         self._decoder.add(self.ram.bus, addr=0x8000000) # SRAM at 0x8000_0000
 
-        # UART at 0xC000_2000
+        # UART at 0xC000_2000, convert 32-bit bus down to 8-bit
         if uart_pins is not None:
-            self.uart = UART16550()
-            umap = MemoryMap(addr_width=7, data_width=8, name="uart_map")
-            #umap.add_resource(self._mem, name="mem", size=1<<5)
-            self.uart.bus.memory_map = umap
-            self._decoder.add(self.uart.bus, addr=0xc0002000) # 16550 UART addr
+            if True:
+                self.uart = uart = UART16550()
+                umap = MemoryMap(addr_width=7, data_width=8, name="uart_map")
+                uart.bus.memory_map = umap
+                self._decoder.add(uart.bus, addr=0xc0002000) # 16550 UART addr
+            else:
+                self.uart = UART16550(data_width=8)
+                cvtuartbus = wishbone.Interface(addr_width=3, data_width=32,
+                                             granularity=8)
+                self.uartdowncvt = WishboneDownConvert(cvtuartbus,
+                                                       self.uart.bus)
+                umap = MemoryMap(addr_width=5, data_width=8, name="uart_map")
+                cvtuartbus.memory_map = umap
+                self._decoder.add(cvtuartbus, addr=0xc0002000) # 16550 UART addr
 
         # DRAM Module
         if ddr_pins is not None:
@@ -144,7 +153,14 @@ class DDR3SoC(SoC, Elaboratable):
             m.submodules.bootmem = self.bootmem
         m.submodules.syscon = self.syscon
         m.submodules.ram = self.ram
-        m.submodules.uart = self.uart
+        if hasattr(self, "uart"):
+            m.submodules.uart = self.uart
+            comb += self.uart.cts_i.eq(1)
+            comb += self.uart.dsr_i.eq(1)
+            comb += self.uart.ri_i.eq(0)
+            comb += self.uart.dcd_i.eq(1)
+        if hasattr(self, "uartdowncvt"):
+            m.submodules.uartdowncvt = self.uartdowncvt
         m.submodules.arbiter = self._arbiter
         m.submodules.decoder = self._decoder
         if hasattr(self, "ddrphy"):