From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 7 Oct 2018 07:03:11 +0000 (+0100)
Subject: add rd bit-setting function
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6da01eab5e40b1e91a7406e6f9ad5ff5ef50793d;p=riscv-isa-sim.git

add rd bit-setting function
---

diff --git a/riscv/sv.cc b/riscv/sv.cc
index 8088ef4..6979e44 100644
--- a/riscv/sv.cc
+++ b/riscv/sv.cc
@@ -189,3 +189,16 @@ uint64_t sv_insn_t::_rvc_spoffs_imm(uint64_t elwidth, uint64_t offs)
   return offs;
 }
 
+// for use in predicated branches. sets bit N if val=true; clears bit N if false
+uint64_t sv_insn_t::rd_bitset(uint64_t bit, bool set)
+{
+    reg_t reg = rd();
+    uint64_t val = READ_REG(reg);
+    if (set) {
+        val |= (1<<bit);
+    } else {
+        val &= ~(1<<bit);
+    }
+    WRITE_REG(reg, val);
+    return val;
+}
diff --git a/riscv/sv_decode.h b/riscv/sv_decode.h
index aa9f952..54ede03 100644
--- a/riscv/sv_decode.h
+++ b/riscv/sv_decode.h
@@ -28,11 +28,13 @@ public:
             offs_rd(o_rd), offs_rs1(o_rs1), offs_rs2(o_rs2), offs_rs3(o_rs3),
             offs_imm(o_imm),
             prd(p_rd), prs1(p_rs1), prs2(p_rs2), prs3(p_rs3) {}
+
   uint64_t _rvc_spoffs_imm(uint64_t elwidth, uint64_t baseoffs);
   uint64_t rvc_lwsp_imm() { return _rvc_spoffs_imm(4, insn_t::rvc_lwsp_imm()); }
   uint64_t rvc_ldsp_imm() { return _rvc_spoffs_imm(8, insn_t::rvc_ldsp_imm()); }
   uint64_t rvc_swsp_imm() { return _rvc_spoffs_imm(4, insn_t::rvc_swsp_imm()); }
   uint64_t rvc_sdsp_imm() { return _rvc_spoffs_imm(8, insn_t::rvc_sdsp_imm()); }
+
   uint64_t rd () { return predicated(_rd (), *offs_rd, prd); }
   uint64_t rs1() { return predicated(_rs1(), *offs_rs1, prs1); }
   uint64_t rs2() { return predicated(_rs2(), *offs_rs2, prs2); }
@@ -55,6 +57,9 @@ public:
   uint64_t _rvc_rs2s() { return _remap(insn_t::rvc_rs2s(), fimap & REG_RVC_RS2S,
                                        offs_rs2); }
 
+  // used for predicated branches. sets bit N if val=true; clears bit N if false
+  uint64_t rd_bitset(uint64_t bit, bool val);
+
   bool sv_check_reg(bool intreg, uint64_t reg);
   sv_reg_entry* get_regentry(uint64_t reg, bool isint);
   sv_pred_entry* get_predentry(uint64_t reg, bool isint);