From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 4 Feb 2022 09:01:06 +0000 (+0100)
Subject: bug fix and cleanups
X-Git-Tag: yosys-0.14~2^2~1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6db23de7b13c57eb82489d4bf2f0658b6deb4488;p=yosys.git

bug fix and cleanups
---

diff --git a/kernel/fstdata.cc b/kernel/fstdata.cc
index 17498c4ee..0b62564f6 100644
--- a/kernel/fstdata.cc
+++ b/kernel/fstdata.cc
@@ -174,7 +174,7 @@ static void reconstruct_clb_attimes(void *user_data, uint64_t pnt_time, fstHandl
 
 void FstData::reconstruct_callback_attimes(uint64_t pnt_time, fstHandle pnt_facidx, const unsigned char *pnt_value, uint32_t /* plen */)
 {
-	if (sample_times_ndx > sample_times.size()) return;
+	if (sample_times_ndx >= sample_times.size()) return;
 
 	uint64_t time = sample_times[sample_times_ndx];
 	// if we are past the timestamp
diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc
index d33c20c51..b2425b531 100644
--- a/passes/sat/sim.cc
+++ b/passes/sat/sim.cc
@@ -752,7 +752,7 @@ struct SimInstance
 			} else if (shared->sim_mode == SimulationMode::gate && !fst_val.is_fully_def()) { // FST data contains X
 				for(int i=0;i<fst_val.size();i++) {
 					if (fst_val[i]!=State::Sx && fst_val[i]!=sim_val[i]) {
-						log_warning("Signal '%s' in file '%s' in simulation '%s'\n", log_id(item.first), log_signal(fst_val), log_signal(sim_val));
+						log_warning("Signal '%s' in file %s in simulation %s\n", log_id(item.first), log_signal(fst_val), log_signal(sim_val));
 						retVal = true;
 						break;
 					}
@@ -760,14 +760,14 @@ struct SimInstance
 			} else if (shared->sim_mode == SimulationMode::gold && !sim_val.is_fully_def()) { // sim data contains X
 				for(int i=0;i<sim_val.size();i++) {
 					if (sim_val[i]!=State::Sx && fst_val[i]!=sim_val[i]) {
-						log_warning("Signal '%s' in file '%s' in simulation '%s'\n", log_id(item.first), log_signal(fst_val), log_signal(sim_val));
+						log_warning("Signal '%s' in file %s in simulation %s\n", log_id(item.first), log_signal(fst_val), log_signal(sim_val));
 						retVal = true;
 						break;
 					}
 				}
 			} else {
 				if (fst_val!=sim_val) {
-					log_warning("Signal '%s' in file '%s' in simulation '%s'\n", log_id(item.first), log_signal(fst_val), log_signal(sim_val));
+					log_warning("Signal '%s' in file %s in simulation '%s'\n", log_id(item.first), log_signal(fst_val), log_signal(sim_val));
 					retVal = true;
 				}
 			}
@@ -1048,9 +1048,9 @@ struct SimWorker : SimShared
 		fst->reconstructAllAtTimes(samples);
 		bool initial = true;
 		int cycle = 0;
-		log("Co-simulation from %zu%s to %zu%s\n", startCount, fst->getTimescaleString(), stopCount, fst->getTimescaleString());
+		log("Co-simulation from %lu%s to %lu%s\n", (unsigned long)startCount, fst->getTimescaleString(), (unsigned long)stopCount, fst->getTimescaleString());
 		for(auto &time : samples) {
-			log("Co-simulating cycle %d [%zu%s].\n", cycle, time, fst->getTimescaleString());
+			log("Co-simulating cycle %d [%lu%s].\n", cycle, (unsigned long)time, fst->getTimescaleString());
 			for(auto &item : inputs) {
 				std::string v = fst->valueAt(item.second, time);
 				top->set_state(item.first, Const::from_string(v));
diff --git a/tests/sat/grom.ys b/tests/sat/grom.ys
index 2c2cd71da..da0f3b620 100644
--- a/tests/sat/grom.ys
+++ b/tests/sat/grom.ys
@@ -1,9 +1,9 @@
 read_verilog grom_computer.v grom_cpu.v alu.v ram_memory.v;
 prep -top grom_computer; 
-sim -clock clk -reset reset -fst grom.fst -vcd grom.vcd -a -n 80
+sim -clock clk -reset reset -fst grom.fst -vcd grom.vcd -n 80
 
 sim -clock clk -r grom.fst -scope grom_computer -start 25ns -stop 100ns -sim-cmp
 
 sim -clock clk -r grom.fst -scope grom_computer -stop 100ns -sim-gold
 
-sim -clock clk -r grom.fst -scope grom_computer -n 10 -sim-gate -a
+sim -clock clk -r grom.fst -scope grom_computer -n 10 -sim-gate