From: Martin Liska <mliska@suse.cz>
Date: Wed, 28 Jun 2017 07:59:23 +0000 (+0200)
Subject: Bail out HARD_REGISTER vars in asan (PR sanitizer/81224).
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6dc61b4533d9b58c10a57761378701e2f9d1b9c0;p=gcc.git

Bail out HARD_REGISTER vars in asan (PR sanitizer/81224).

2017-06-28  Martin Liska  <mliska@suse.cz>

	PR sanitizer/81224
	* asan.c (instrument_derefs): Bail out inner references
	that are hard register variables.
2017-06-28  Martin Liska  <mliska@suse.cz>

	PR sanitizer/81224
	* gcc.dg/asan/pr81224.c: New test.

From-SVN: r249728
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index ff71efad23e..a70b03dd9ed 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2017-06-28  Martin Liska  <mliska@suse.cz>
+
+	PR sanitizer/81224
+	* asan.c (instrument_derefs): Bail out inner references
+	that are hard register variables.
+
 2017-06-28  Jakub Jelinek  <jakub@redhat.com>
 
 	PR target/81175
diff --git a/gcc/asan.c b/gcc/asan.c
index e730530930b..3f814819add 100644
--- a/gcc/asan.c
+++ b/gcc/asan.c
@@ -1875,6 +1875,9 @@ instrument_derefs (gimple_stmt_iterator *iter, tree t,
       || bitsize != size_in_bytes * BITS_PER_UNIT)
     return;
 
+  if (VAR_P (inner) && DECL_HARD_REGISTER (inner))
+    return;
+
   if (VAR_P (inner)
       && offset == NULL_TREE
       && bitpos >= 0
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index f2f9a3e1b89..178b23666a8 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2017-06-28  Martin Liska  <mliska@suse.cz>
+
+	PR sanitizer/81224
+	* gcc.dg/asan/pr81224.c: New test.
+
 2017-06-28  Eric Botcazou  <ebotcazou@adacore.com>
 
 	* gcc.dg/tree-prof/val-profiler-threads-1.c (main): Fix 2nd argument
diff --git a/gcc/testsuite/gcc.dg/asan/pr81224.c b/gcc/testsuite/gcc.dg/asan/pr81224.c
new file mode 100644
index 00000000000..def5cb69aec
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/asan/pr81224.c
@@ -0,0 +1,11 @@
+/* PR sanitizer/80659 */
+/* { dg-do compile { target { i?86-*-* x86_64-*-* } } } */
+/* { dg-additional-options "-msse2" } */
+
+int a;
+int
+b ()
+{
+  register __attribute__ ((__vector_size__ (4 * sizeof (int)))) int c asm("xmm0");
+  return c[a];
+}