From: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Date: Thu, 21 May 2020 19:48:03 +0000 (-0400)
Subject: panfrost: Limit blend shader work count
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6dd11a6dc34c624a90de3e064ad3552830a8d0d9;p=mesa.git

panfrost: Limit blend shader work count

To 8, but later we should go much lower.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5124>
---

diff --git a/src/gallium/drivers/panfrost/pan_cmdstream.c b/src/gallium/drivers/panfrost/pan_cmdstream.c
index 50eaa195a69..21ab118085d 100644
--- a/src/gallium/drivers/panfrost/pan_cmdstream.c
+++ b/src/gallium/drivers/panfrost/pan_cmdstream.c
@@ -642,12 +642,15 @@ panfrost_frag_meta_blend_update(struct panfrost_context *ctx,
                 blend[c] = panfrost_get_blend_for_context(ctx, c, &shader_bo,
                                                           &shader_offset);
 
-         /* If there is a blend shader, work registers are shared. XXX: opt */
+         /* If there is a blend shader, work registers are shared. We impose 8
+          * work registers as a limit for blend shaders. Should be lower XXX */
 
         if (!(dev->quirks & IS_BIFROST)) {
                 for (unsigned c = 0; c < rt_count; ++c) {
-                        if (blend[c].is_shader)
-                                fragmeta->midgard1.work_count = 16;
+                        if (blend[c].is_shader) {
+                                fragmeta->midgard1.work_count =
+                                        MAX2(fragmeta->midgard1.work_count, 8);
+                        }
                 }
         }
 
diff --git a/src/panfrost/midgard/midgard_ra.c b/src/panfrost/midgard/midgard_ra.c
index baeec45f042..8c6210e0634 100644
--- a/src/panfrost/midgard/midgard_ra.c
+++ b/src/panfrost/midgard/midgard_ra.c
@@ -442,8 +442,10 @@ static struct lcra_state *
 allocate_registers(compiler_context *ctx, bool *spilled)
 {
         /* The number of vec4 work registers available depends on when the
-         * uniforms start, so compute that first */
-        int work_count = 16 - MAX2((ctx->uniform_cutoff - 8), 0);
+         * uniforms start and the shader stage. By ABI we limit blend shaders
+         * to 8 registers, should be lower XXX */
+        int work_count = ctx->is_blend ? 8 :
+                16 - MAX2((ctx->uniform_cutoff - 8), 0);
 
        /* No register allocation to do with no SSA */
 
@@ -831,6 +833,9 @@ mir_spill_register(
                 unsigned spill_class,
                 unsigned *spill_count)
 {
+        if (spill_class == REG_CLASS_WORK && ctx->is_blend)
+                unreachable("Blend shader spilling is currently unimplemented");
+
         unsigned spill_index = ctx->temp_count;
 
         /* We have a spill node, so check the class. Work registers