From: Clifford Wolf Date: Tue, 9 Jul 2019 20:51:25 +0000 (+0200) Subject: Merge pull request #1175 from whitequark/write_verilog-fix-case-attr-position X-Git-Tag: working-ls180~1212 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6dd33be7cec561675be362301ba837cb41f7c283;p=yosys.git Merge pull request #1175 from whitequark/write_verilog-fix-case-attr-position write_verilog: fix placement of case attributes --- 6dd33be7cec561675be362301ba837cb41f7c283