From: lkcl <lkcl@web>
Date: Thu, 21 Apr 2022 08:20:02 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2662
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6dd57e63b2ab17b8f7d941a1bf52b33c8eac1df3;p=libreriscv.git

---

diff --git a/openpower/sv/biginteger.mdwn b/openpower/sv/biginteger.mdwn
index 52735f50c..38ba735e7 100644
--- a/openpower/sv/biginteger.mdwn
+++ b/openpower/sv/biginteger.mdwn
@@ -20,7 +20,7 @@ Dynamic SIMD ALUs for maximum performance and effectiveness.
 
 # Analysis
 
-Covered in [[analysis]] the summary is that standard `adde` is sufficient
+Covered in [[biginteger/analysis]] the summary is that standard `adde` is sufficient
 for SVP64 Vectorisation, but that big-integer multiply and divide
 require two extra 3-in 2-out instructions, similar to Intel's `mulx`.