From: Andrew Waterman <waterman@cs.berkeley.edu>
Date: Sat, 13 Jul 2013 01:20:16 +0000 (-0700)
Subject: Fix SR_U64 bit being ignored
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6de0c1e324745f426d5ff3c30af2acbe10042ceb;p=riscv-isa-sim.git

Fix SR_U64 bit being ignored
---

diff --git a/riscv/dispatch b/riscv/dispatch
index 231853c..5afc3be 100755
--- a/riscv/dispatch
+++ b/riscv/dispatch
@@ -49,7 +49,7 @@ if filenum == numfiles:
 
 if filenum == numfiles+1:
   print '#define get_insn_func(insn, sr) \\'
-  print '  processor_t::dispatch_table[((((sr) & SR_S) ? (sr & SR_S64) : (SR_U64)) ? %d : 0) + ((insn).bits %% %d)]' % (tablesz, tablesz)
+  print '  processor_t::dispatch_table[((((sr) & SR_S) ? (sr & SR_S64) : (sr & SR_U64)) ? %d : 0) + ((insn).bits %% %d)]' % (tablesz, tablesz)
   
   print 'static const insn_func_t dispatch_table[%d];' % (2*tablesz)
   for i in range(0, tablesz):