From: Nelson Chu Date: Thu, 7 Sep 2023 02:52:25 +0000 (+0800) Subject: RISC-V: Clarify the naming rules of vendor operands. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6de11ff67a925a496319d25dee0bea58427aacf6;p=binutils-gdb.git RISC-V: Clarify the naming rules of vendor operands. The vendor operands should be named starting with `X', and preferably the second letter (or multiple following letters) is enough to differentiate them from other vendors. Therefore, added letter `t' after `X' for t-head operands, to differentiate from future different vendor's operands. bfd/ * elfxx-riscv.c (riscv_supported_vendor_x_ext): Removed the vendor document link since it should already be recorded in the gas/doc/c-riscv.texi. gas/ * config/tc-riscv.c (validate_riscv_insn): Added `t' after `X' for t-head operands. Minor updates for indents and comments. (riscv_ip): Likewise. * doc/c-riscv.texi: Minor updates. opcodes/ * riscv-dis.c (print_insn_args): Added `t' after `X' for t-head operands. Minor updates for indents and comments. * riscv-opc.c (riscv_opcode): Likewise. --- diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index e642a05fe5b..6ed657171f0 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1363,7 +1363,6 @@ static struct riscv_supported_ext riscv_supported_vendor_x_ext[] = {"xtheadmemidx", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xtheadmempair", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xtheadsync", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - /* XVentanaCondOps: https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf */ {"xventanacondops", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {NULL, 0, 0, 0, 0} }; diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index e3bcf8b280e..cf6e0d8b015 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -1400,23 +1400,23 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length) case 'F': /* Funct for .insn directive. */ switch (*++oparg) { - case '7': USE_BITS (OP_MASK_FUNCT7, OP_SH_FUNCT7); break; - case '3': USE_BITS (OP_MASK_FUNCT3, OP_SH_FUNCT3); break; - case '2': USE_BITS (OP_MASK_FUNCT2, OP_SH_FUNCT2); break; - default: - goto unknown_validate_operand; + case '7': USE_BITS (OP_MASK_FUNCT7, OP_SH_FUNCT7); break; + case '3': USE_BITS (OP_MASK_FUNCT3, OP_SH_FUNCT3); break; + case '2': USE_BITS (OP_MASK_FUNCT2, OP_SH_FUNCT2); break; + default: + goto unknown_validate_operand; } break; case 'O': /* Opcode for .insn directive. */ switch (*++oparg) { - case '4': USE_BITS (OP_MASK_OP, OP_SH_OP); break; - case '2': USE_BITS (OP_MASK_OP2, OP_SH_OP2); break; - default: - goto unknown_validate_operand; + case '4': USE_BITS (OP_MASK_OP, OP_SH_OP); break; + case '2': USE_BITS (OP_MASK_OP2, OP_SH_OP2); break; + default: + goto unknown_validate_operand; } break; - case 'W': /* Various operands. */ + case 'W': /* Various operands for standard z extensions. */ switch (*++oparg) { case 'i': @@ -1451,33 +1451,39 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length) goto unknown_validate_operand; } break; - case 'X': /* Integer immediate. */ - { - size_t n; - size_t s; - - switch (*++oparg) + case 'X': /* Vendor-specific operands. */ + switch (*++oparg) + { + case 't': /* Vendor-specific (T-head) operands. */ { - case 'l': /* Literal. */ - oparg += strcspn(oparg, ",") - 1; - break; - case 's': /* 'XsN@S' ... N-bit signed immediate at bit S. */ - goto use_imm; - case 'u': /* 'XuN@S' ... N-bit unsigned immediate at bit S. */ - goto use_imm; - use_imm: - n = strtol (oparg + 1, (char **)&oparg, 10); - if (*oparg != '@') + size_t n; + size_t s; + switch (*++oparg) + { + case 'l': /* Integer immediate, literal. */ + oparg += strcspn(oparg, ",") - 1; + break; + case 's': /* Integer immediate, 'XtsN@S' ... N-bit signed immediate at bit S. */ + goto use_imm; + case 'u': /* Integer immediate, 'XtuN@S' ... N-bit unsigned immediate at bit S. */ + goto use_imm; + use_imm: + n = strtol (oparg + 1, (char **)&oparg, 10); + if (*oparg != '@') + goto unknown_validate_operand; + s = strtol (oparg + 1, (char **)&oparg, 10); + oparg--; + + USE_IMM (n, s); + break; + default: goto unknown_validate_operand; - s = strtol (oparg + 1, (char **)&oparg, 10); - oparg--; - - USE_IMM (n, s); - break; - default: - goto unknown_validate_operand; + } } - } + break; + default: + goto unknown_validate_operand; + } break; default: unknown_validate_operand: @@ -3489,7 +3495,7 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr, imm_expr->X_op = O_absent; continue; - case 'W': /* Various operands. */ + case 'W': /* Various operands for standard z extensions. */ switch (*++oparg) { case 'i': @@ -3516,6 +3522,7 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr, goto unknown_riscv_ip_operand; } break; + case 'f': switch (*++oparg) { @@ -3559,7 +3566,6 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr, break; ip->insn_opcode |= ENCODE_ZCB_HALFWORD_UIMM (imm_expr->X_add_number); goto rvc_imm_done; - case 'b': /* Immediate field for c.lbu/c.sb. */ /* Handle cases, such as c.lbu rd', (rs1'). */ if (riscv_handle_implicit_zero_offset (imm_expr, asarg)) @@ -3570,7 +3576,6 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr, break; ip->insn_opcode |= ENCODE_ZCB_BYTE_UIMM (imm_expr->X_add_number); goto rvc_imm_done; - case 'f': /* Operand for matching immediate 255. */ if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p) || imm_expr->X_op != O_constant @@ -3581,66 +3586,73 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr, asarg = expr_parse_end; imm_expr->X_op = O_absent; continue; - default: goto unknown_riscv_ip_operand; } break; + default: goto unknown_riscv_ip_operand; } break; - case 'X': /* Integer immediate. */ - { - size_t n; - size_t s; - bool sign; - - switch (*++oparg) + case 'X': /* Vendor-specific operands. */ + switch (*++oparg) + { + case 't': /* Vendor-specific (T-head) operands. */ { - case 'l': /* Literal. */ - n = strcspn (++oparg, ","); - if (strncmp (oparg, asarg, n)) - as_bad (_("unexpected literal (%s)"), asarg); - oparg += n - 1; - asarg += n; - continue; - case 's': /* 'XsN@S' ... N-bit signed immediate at bit S. */ - sign = true; - goto parse_imm; - case 'u': /* 'XuN@S' ... N-bit unsigned immediate at bit S. */ - sign = false; - goto parse_imm; - parse_imm: - n = strtol (oparg + 1, (char **)&oparg, 10); - if (*oparg != '@') + size_t n; + size_t s; + bool sign; + switch (*++oparg) + { + case 'l': /* Integer immediate, literal. */ + n = strcspn (++oparg, ","); + if (strncmp (oparg, asarg, n)) + as_bad (_("unexpected literal (%s)"), asarg); + oparg += n - 1; + asarg += n; + continue; + case 's': /* Integer immediate, 'XsN@S' ... N-bit signed immediate at bit S. */ + sign = true; + goto parse_imm; + case 'u': /* Integer immediate, 'XuN@S' ... N-bit unsigned immediate at bit S. */ + sign = false; + goto parse_imm; + parse_imm: + n = strtol (oparg + 1, (char **)&oparg, 10); + if (*oparg != '@') + goto unknown_riscv_ip_operand; + s = strtol (oparg + 1, (char **)&oparg, 10); + oparg--; + + my_getExpression (imm_expr, asarg); + check_absolute_expr (ip, imm_expr, false); + if (!sign) + { + if (!VALIDATE_U_IMM (imm_expr->X_add_number, n)) + as_bad (_("improper immediate value (%"PRIu64")"), + imm_expr->X_add_number); + } + else + { + if (!VALIDATE_S_IMM (imm_expr->X_add_number, n)) + as_bad (_("improper immediate value (%"PRIi64")"), + imm_expr->X_add_number); + } + INSERT_IMM (n, s, *ip, imm_expr->X_add_number); + imm_expr->X_op = O_absent; + asarg = expr_parse_end; + continue; + default: goto unknown_riscv_ip_operand; - s = strtol (oparg + 1, (char **)&oparg, 10); - oparg--; - - my_getExpression (imm_expr, asarg); - check_absolute_expr (ip, imm_expr, false); - if (!sign) - { - if (!VALIDATE_U_IMM (imm_expr->X_add_number, n)) - as_bad (_("improper immediate value (%"PRIu64")"), - imm_expr->X_add_number); - } - else - { - if (!VALIDATE_S_IMM (imm_expr->X_add_number, n)) - as_bad (_("improper immediate value (%"PRIi64")"), - imm_expr->X_add_number); - } - INSERT_IMM (n, s, *ip, imm_expr->X_add_number); - imm_expr->X_op = O_absent; - asarg = expr_parse_end; - continue; - default: - goto unknown_riscv_ip_operand; + } } - } + break; + + default: + goto unknown_riscv_ip_operand; + } break; default: diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi index b175ba0a729..7921556a4f7 100644 --- a/gas/doc/c-riscv.texi +++ b/gas/doc/c-riscv.texi @@ -804,11 +804,12 @@ It is documented in @url{https://github.com/T-head-Semi/thead-extension-spec/rel The XTheadSync extension provides instructions for multi-processor synchronization. It is documented in @url{https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf}. + @item XVentanaCondOps XVentanaCondOps extension provides instructions for branchless sequences that perform conditional arithmetic, conditional bitwise-logic, and conditional select operations. -It is documented at @url{https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf}. +It is documented in @url{https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf}. @end table diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c index 90f0fea1692..c0fd0625a2d 100644 --- a/opcodes/riscv-dis.c +++ b/opcodes/riscv-dis.c @@ -584,97 +584,102 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info print (info->stream, dis_style_immediate, "%d", rs1); break; - case 'W': /* Various operands. */ - { - switch (*++oparg) + case 'W': /* Various operands for standard z extensions. */ + switch (*++oparg) + { + case 'i': + switch (*++oparg) + { + case 'f': + print (info->stream, dis_style_address_offset, "%d", + (int) EXTRACT_STYPE_IMM (l)); + break; + default: + goto undefined_modifier; + } + break; + case 'f': + switch (*++oparg) + { + case 'v': + if (riscv_fli_symval[rs1]) + print (info->stream, dis_style_text, "%s", + riscv_fli_symval[rs1]); + else + print (info->stream, dis_style_immediate, "%a", + riscv_fli_numval[rs1]); + break; + default: + goto undefined_modifier; + } + break; + case 'c': /* Zcb extension 16 bits length instruction fields. */ + switch (*++oparg) + { + case 'b': + print (info->stream, dis_style_immediate, "%d", + (int)EXTRACT_ZCB_BYTE_UIMM (l)); + break; + case 'h': + print (info->stream, dis_style_immediate, "%d", + (int)EXTRACT_ZCB_HALFWORD_UIMM (l)); + break; + default: + goto undefined_modifier; + } + break; + default: + goto undefined_modifier; + } + break; + + case 'X': /* Vendor-specific operands. */ + switch (*++oparg) + { + case 't': /* Vendor-specific (T-head) operands. */ { - case 'i': + size_t n; + size_t s; + bool sign; switch (*++oparg) { - case 'f': - print (info->stream, dis_style_address_offset, "%d", - (int) EXTRACT_STYPE_IMM (l)); + case 'l': /* Integer immediate, literal. */ + oparg++; + while (*oparg && *oparg != ',') + { + print (info->stream, dis_style_immediate, "%c", *oparg); + oparg++; + } + oparg--; break; - default: - goto undefined_modifier; - } - break; - case 'f': - switch (*++oparg) - { - case 'v': - if (riscv_fli_symval[rs1]) - print (info->stream, dis_style_text, "%s", - riscv_fli_symval[rs1]); + case 's': /* Integer immediate, 'XsN@S' ... N-bit signed immediate at bit S. */ + sign = true; + goto print_imm; + case 'u': /* Integer immediate, 'XuN@S' ... N-bit unsigned immediate at bit S. */ + sign = false; + goto print_imm; + print_imm: + n = strtol (oparg + 1, (char **)&oparg, 10); + if (*oparg != '@') + goto undefined_modifier; + s = strtol (oparg + 1, (char **)&oparg, 10); + oparg--; + + if (!sign) + print (info->stream, dis_style_immediate, "%lu", + (unsigned long)EXTRACT_U_IMM (n, s, l)); else - print (info->stream, dis_style_immediate, "%a", - riscv_fli_numval[rs1]); + print (info->stream, dis_style_immediate, "%li", + (signed long)EXTRACT_S_IMM (n, s, l)); break; default: goto undefined_modifier; } - break; - case 'c': /* Zcb extension 16 bits length instruction fields. */ - switch (*++oparg) - { - case 'b': - print (info->stream, dis_style_immediate, "%d", - (int)EXTRACT_ZCB_BYTE_UIMM (l)); - break; - case 'h': - print (info->stream, dis_style_immediate, "%d", - (int)EXTRACT_ZCB_HALFWORD_UIMM (l)); - break; - default: break; - } - break; - default: - goto undefined_modifier; - } - } - break; - - case 'X': /* Integer immediate. */ - { - size_t n; - size_t s; - bool sign; - - switch (*++oparg) - { - case 'l': /* Literal. */ - oparg++; - while (*oparg && *oparg != ',') - { - print (info->stream, dis_style_immediate, "%c", *oparg); - oparg++; - } - oparg--; - break; - case 's': /* 'XsN@S' ... N-bit signed immediate at bit S. */ - sign = true; - goto print_imm; - case 'u': /* 'XuN@S' ... N-bit unsigned immediate at bit S. */ - sign = false; - goto print_imm; - print_imm: - n = strtol (oparg + 1, (char **)&oparg, 10); - if (*oparg != '@') - goto undefined_modifier; - s = strtol (oparg + 1, (char **)&oparg, 10); - oparg--; - - if (!sign) - print (info->stream, dis_style_immediate, "%lu", - (unsigned long)EXTRACT_U_IMM (n, s, l)); - else - print (info->stream, dis_style_immediate, "%li", - (signed long)EXTRACT_S_IMM (n, s, l)); - break; - default: - goto undefined_modifier; } - } + break; + default: + goto undefined_modifier; + } break; default: diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 243ec6670ba..8e0ae85eb06 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -2040,13 +2040,13 @@ const struct riscv_opcode riscv_opcodes[] = {"hsv.d", 64, INSN_CLASS_H, "t,0(s)", MATCH_HSV_D, MASK_HSV_D, match_opcode, INSN_DREF|INSN_8_BYTE }, /* Vendor-specific (T-Head) XTheadBa instructions. */ -{"th.addsl", 0, INSN_CLASS_XTHEADBA, "d,s,t,Xu2@25", MATCH_TH_ADDSL, MASK_TH_ADDSL, match_opcode, 0}, +{"th.addsl", 0, INSN_CLASS_XTHEADBA, "d,s,t,Xtu2@25", MATCH_TH_ADDSL, MASK_TH_ADDSL, match_opcode, 0}, /* Vendor-specific (T-Head) XTheadBb instructions. */ -{"th.srri", 0, INSN_CLASS_XTHEADBB, "d,s,Xu6@20", MATCH_TH_SRRI, MASK_TH_SRRI, match_opcode, 0}, -{"th.srriw", 64, INSN_CLASS_XTHEADBB, "d,s,Xu5@20", MATCH_TH_SRRIW, MASK_TH_SRRIW, match_opcode, 0}, -{"th.ext", 0, INSN_CLASS_XTHEADBB, "d,s,Xu6@26,Xu6@20", MATCH_TH_EXT, MASK_TH_EXT, match_opcode, 0}, -{"th.extu", 0, INSN_CLASS_XTHEADBB, "d,s,Xu6@26,Xu6@20", MATCH_TH_EXTU, MASK_TH_EXTU, match_opcode, 0}, +{"th.srri", 0, INSN_CLASS_XTHEADBB, "d,s,Xtu6@20", MATCH_TH_SRRI, MASK_TH_SRRI, match_opcode, 0}, +{"th.srriw", 64, INSN_CLASS_XTHEADBB, "d,s,Xtu5@20", MATCH_TH_SRRIW, MASK_TH_SRRIW, match_opcode, 0}, +{"th.ext", 0, INSN_CLASS_XTHEADBB, "d,s,Xtu6@26,Xtu6@20", MATCH_TH_EXT, MASK_TH_EXT, match_opcode, 0}, +{"th.extu", 0, INSN_CLASS_XTHEADBB, "d,s,Xtu6@26,Xtu6@20", MATCH_TH_EXTU, MASK_TH_EXTU, match_opcode, 0}, {"th.ff0", 0, INSN_CLASS_XTHEADBB, "d,s", MATCH_TH_FF0, MASK_TH_FF0, match_opcode, 0}, {"th.ff1", 0, INSN_CLASS_XTHEADBB, "d,s", MATCH_TH_FF1, MASK_TH_FF1, match_opcode, 0}, {"th.rev", 0, INSN_CLASS_XTHEADBB, "d,s", MATCH_TH_REV, MASK_TH_REV, match_opcode, 0}, @@ -2054,7 +2054,7 @@ const struct riscv_opcode riscv_opcodes[] = {"th.tstnbz", 0, INSN_CLASS_XTHEADBB, "d,s", MATCH_TH_TSTNBZ, MASK_TH_TSTNBZ, match_opcode, 0}, /* Vendor-specific (T-Head) XTheadBs instructions. */ -{"th.tst", 0, INSN_CLASS_XTHEADBS, "d,s,Xu6@20", MATCH_TH_TST, MASK_TH_TST, match_opcode, 0}, +{"th.tst", 0, INSN_CLASS_XTHEADBS, "d,s,Xtu6@20", MATCH_TH_TST, MASK_TH_TST, match_opcode, 0}, /* Vendor-specific (T-Head) XTheadCmo instructions. */ {"th.dcache.call", 0, INSN_CLASS_XTHEADCMO, "", MATCH_TH_DCACHE_CALL, MASK_TH_DCACHE_CALL, match_opcode, 0}, @@ -2086,14 +2086,14 @@ const struct riscv_opcode riscv_opcodes[] = {"th.mvnez", 0, INSN_CLASS_XTHEADCONDMOV, "d,s,t", MATCH_TH_MVNEZ, MASK_TH_MVNEZ, match_opcode, 0}, /* Vendor-specific (T-Head) XTheadFMemIdx instructions. */ -{"th.flrd", 0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xu2@25", MATCH_TH_FLRD, MASK_TH_FLRD, match_opcode, 0}, -{"th.flrw", 0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xu2@25", MATCH_TH_FLRW, MASK_TH_FLRW, match_opcode, 0}, -{"th.flurd", 0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xu2@25", MATCH_TH_FLURD, MASK_TH_FLURD, match_opcode, 0}, -{"th.flurw", 0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xu2@25", MATCH_TH_FLURW, MASK_TH_FLURW, match_opcode, 0}, -{"th.fsrd", 0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xu2@25", MATCH_TH_FSRD, MASK_TH_FSRD, match_opcode, 0}, -{"th.fsrw", 0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xu2@25", MATCH_TH_FSRW, MASK_TH_FSRW, match_opcode, 0}, -{"th.fsurd", 0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xu2@25", MATCH_TH_FSURD, MASK_TH_FSURD, match_opcode, 0}, -{"th.fsurw", 0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xu2@25", MATCH_TH_FSURW, MASK_TH_FSURW, match_opcode, 0}, +{"th.flrd", 0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xtu2@25", MATCH_TH_FLRD, MASK_TH_FLRD, match_opcode, 0}, +{"th.flrw", 0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xtu2@25", MATCH_TH_FLRW, MASK_TH_FLRW, match_opcode, 0}, +{"th.flurd", 0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xtu2@25", MATCH_TH_FLURD, MASK_TH_FLURD, match_opcode, 0}, +{"th.flurw", 0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xtu2@25", MATCH_TH_FLURW, MASK_TH_FLURW, match_opcode, 0}, +{"th.fsrd", 0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xtu2@25", MATCH_TH_FSRD, MASK_TH_FSRD, match_opcode, 0}, +{"th.fsrw", 0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xtu2@25", MATCH_TH_FSRW, MASK_TH_FSRW, match_opcode, 0}, +{"th.fsurd", 0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xtu2@25", MATCH_TH_FSURD, MASK_TH_FSURD, match_opcode, 0}, +{"th.fsurw", 0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xtu2@25", MATCH_TH_FSURW, MASK_TH_FSURW, match_opcode, 0}, /* Vendor-specific (T-Head) XTheadFmv instructions. */ {"th.fmv.hw.x", 32, INSN_CLASS_XTHEADFMV, "d,S", MATCH_TH_FMV_HW_X, MASK_TH_FMV_HW_X, match_opcode, 0}, @@ -2104,59 +2104,59 @@ const struct riscv_opcode riscv_opcodes[] = {"th.ipush", 0, INSN_CLASS_XTHEADINT, "", MATCH_TH_IPUSH, MASK_TH_IPUSH, match_opcode, 0}, /* Vendor-specific (T-Head) XTheadMemIdx instructions. */ -{"th.ldia", 64, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", MATCH_TH_LDIA, MASK_TH_LDIA, match_th_load_inc, 0}, -{"th.ldib", 64, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", MATCH_TH_LDIB, MASK_TH_LDIB, match_th_load_inc, 0}, -{"th.lwia", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", MATCH_TH_LWIA, MASK_TH_LWIA, match_th_load_inc, 0}, -{"th.lwib", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", MATCH_TH_LWIB, MASK_TH_LWIB, match_th_load_inc, 0}, -{"th.lwuia", 64, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", MATCH_TH_LWUIA, MASK_TH_LWUIA, match_th_load_inc, 0}, -{"th.lwuib", 64, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", MATCH_TH_LWUIB, MASK_TH_LWUIB, match_th_load_inc, 0}, -{"th.lhia", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", MATCH_TH_LHIA, MASK_TH_LHIA, match_th_load_inc, 0}, -{"th.lhib", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", MATCH_TH_LHIB, MASK_TH_LHIB, match_th_load_inc, 0}, -{"th.lhuia", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", MATCH_TH_LHUIA, MASK_TH_LHUIA, match_th_load_inc, 0}, -{"th.lhuib", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", MATCH_TH_LHUIB, MASK_TH_LHUIB, match_th_load_inc, 0}, -{"th.lbia", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", MATCH_TH_LBIA, MASK_TH_LBIA, match_th_load_inc, 0}, -{"th.lbib", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", MATCH_TH_LBIB, MASK_TH_LBIB, match_th_load_inc, 0}, -{"th.lbuia", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", MATCH_TH_LBUIA, MASK_TH_LBUIA, match_th_load_inc, 0}, -{"th.lbuib", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", MATCH_TH_LBUIB, MASK_TH_LBUIB, match_th_load_inc, 0}, -{"th.sdia", 64, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", MATCH_TH_SDIA, MASK_TH_SDIA, match_opcode, 0}, -{"th.sdib", 64, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", MATCH_TH_SDIB, MASK_TH_SDIB, match_opcode, 0}, -{"th.swia", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", MATCH_TH_SWIA, MASK_TH_SWIA, match_opcode, 0}, -{"th.swib", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", MATCH_TH_SWIB, MASK_TH_SWIB, match_opcode, 0}, -{"th.shia", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", MATCH_TH_SHIA, MASK_TH_SHIA, match_opcode, 0}, -{"th.shib", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", MATCH_TH_SHIB, MASK_TH_SHIB, match_opcode, 0}, -{"th.sbia", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", MATCH_TH_SBIA, MASK_TH_SBIA, match_opcode, 0}, -{"th.sbib", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", MATCH_TH_SBIB, MASK_TH_SBIB, match_opcode, 0}, - -{"th.lrd", 64, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", MATCH_TH_LRD, MASK_TH_LRD, match_opcode, 0}, -{"th.lrw", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", MATCH_TH_LRW, MASK_TH_LRW, match_opcode, 0}, -{"th.lrwu", 64, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", MATCH_TH_LRWU, MASK_TH_LRWU, match_opcode, 0}, -{"th.lrh", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", MATCH_TH_LRH, MASK_TH_LRH, match_opcode, 0}, -{"th.lrhu", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", MATCH_TH_LRHU, MASK_TH_LRHU, match_opcode, 0}, -{"th.lrb", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", MATCH_TH_LRB, MASK_TH_LRB, match_opcode, 0}, -{"th.lrbu", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", MATCH_TH_LRBU, MASK_TH_LRBU, match_opcode, 0}, -{"th.srd", 64, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", MATCH_TH_SRD, MASK_TH_SRD, match_opcode, 0}, -{"th.srw", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", MATCH_TH_SRW, MASK_TH_SRW, match_opcode, 0}, -{"th.srh", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", MATCH_TH_SRH, MASK_TH_SRH, match_opcode, 0}, -{"th.srb", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", MATCH_TH_SRB, MASK_TH_SRB, match_opcode, 0}, - -{"th.lurd", 64, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", MATCH_TH_LURD, MASK_TH_LURD, match_opcode, 0}, -{"th.lurw", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", MATCH_TH_LURW, MASK_TH_LURW, match_opcode, 0}, -{"th.lurwu", 64, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", MATCH_TH_LURWU, MASK_TH_LURWU, match_opcode, 0}, -{"th.lurh", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", MATCH_TH_LURH, MASK_TH_LURH, match_opcode, 0}, -{"th.lurhu", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", MATCH_TH_LURHU, MASK_TH_LURHU, match_opcode, 0}, -{"th.lurb", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", MATCH_TH_LURB, MASK_TH_LURB, match_opcode, 0}, -{"th.lurbu", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", MATCH_TH_LURBU, MASK_TH_LURBU, match_opcode, 0}, -{"th.surd", 64, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", MATCH_TH_SURD, MASK_TH_SURD, match_opcode, 0}, -{"th.surw", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", MATCH_TH_SURW, MASK_TH_SURW, match_opcode, 0}, -{"th.surh", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", MATCH_TH_SURH, MASK_TH_SURH, match_opcode, 0}, -{"th.surb", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", MATCH_TH_SURB, MASK_TH_SURB, match_opcode, 0}, +{"th.ldia", 64, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_LDIA, MASK_TH_LDIA, match_th_load_inc, 0}, +{"th.ldib", 64, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_LDIB, MASK_TH_LDIB, match_th_load_inc, 0}, +{"th.lwia", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_LWIA, MASK_TH_LWIA, match_th_load_inc, 0}, +{"th.lwib", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_LWIB, MASK_TH_LWIB, match_th_load_inc, 0}, +{"th.lwuia", 64, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_LWUIA, MASK_TH_LWUIA, match_th_load_inc, 0}, +{"th.lwuib", 64, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_LWUIB, MASK_TH_LWUIB, match_th_load_inc, 0}, +{"th.lhia", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_LHIA, MASK_TH_LHIA, match_th_load_inc, 0}, +{"th.lhib", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_LHIB, MASK_TH_LHIB, match_th_load_inc, 0}, +{"th.lhuia", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_LHUIA, MASK_TH_LHUIA, match_th_load_inc, 0}, +{"th.lhuib", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_LHUIB, MASK_TH_LHUIB, match_th_load_inc, 0}, +{"th.lbia", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_LBIA, MASK_TH_LBIA, match_th_load_inc, 0}, +{"th.lbib", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_LBIB, MASK_TH_LBIB, match_th_load_inc, 0}, +{"th.lbuia", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_LBUIA, MASK_TH_LBUIA, match_th_load_inc, 0}, +{"th.lbuib", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_LBUIB, MASK_TH_LBUIB, match_th_load_inc, 0}, +{"th.sdia", 64, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_SDIA, MASK_TH_SDIA, match_opcode, 0}, +{"th.sdib", 64, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_SDIB, MASK_TH_SDIB, match_opcode, 0}, +{"th.swia", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_SWIA, MASK_TH_SWIA, match_opcode, 0}, +{"th.swib", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_SWIB, MASK_TH_SWIB, match_opcode, 0}, +{"th.shia", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_SHIA, MASK_TH_SHIA, match_opcode, 0}, +{"th.shib", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_SHIB, MASK_TH_SHIB, match_opcode, 0}, +{"th.sbia", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_SBIA, MASK_TH_SBIA, match_opcode, 0}, +{"th.sbib", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_SBIB, MASK_TH_SBIB, match_opcode, 0}, + +{"th.lrd", 64, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xtu2@25", MATCH_TH_LRD, MASK_TH_LRD, match_opcode, 0}, +{"th.lrw", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xtu2@25", MATCH_TH_LRW, MASK_TH_LRW, match_opcode, 0}, +{"th.lrwu", 64, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xtu2@25", MATCH_TH_LRWU, MASK_TH_LRWU, match_opcode, 0}, +{"th.lrh", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xtu2@25", MATCH_TH_LRH, MASK_TH_LRH, match_opcode, 0}, +{"th.lrhu", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xtu2@25", MATCH_TH_LRHU, MASK_TH_LRHU, match_opcode, 0}, +{"th.lrb", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xtu2@25", MATCH_TH_LRB, MASK_TH_LRB, match_opcode, 0}, +{"th.lrbu", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xtu2@25", MATCH_TH_LRBU, MASK_TH_LRBU, match_opcode, 0}, +{"th.srd", 64, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xtu2@25", MATCH_TH_SRD, MASK_TH_SRD, match_opcode, 0}, +{"th.srw", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xtu2@25", MATCH_TH_SRW, MASK_TH_SRW, match_opcode, 0}, +{"th.srh", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xtu2@25", MATCH_TH_SRH, MASK_TH_SRH, match_opcode, 0}, +{"th.srb", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xtu2@25", MATCH_TH_SRB, MASK_TH_SRB, match_opcode, 0}, + +{"th.lurd", 64, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xtu2@25", MATCH_TH_LURD, MASK_TH_LURD, match_opcode, 0}, +{"th.lurw", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xtu2@25", MATCH_TH_LURW, MASK_TH_LURW, match_opcode, 0}, +{"th.lurwu", 64, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xtu2@25", MATCH_TH_LURWU, MASK_TH_LURWU, match_opcode, 0}, +{"th.lurh", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xtu2@25", MATCH_TH_LURH, MASK_TH_LURH, match_opcode, 0}, +{"th.lurhu", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xtu2@25", MATCH_TH_LURHU, MASK_TH_LURHU, match_opcode, 0}, +{"th.lurb", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xtu2@25", MATCH_TH_LURB, MASK_TH_LURB, match_opcode, 0}, +{"th.lurbu", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xtu2@25", MATCH_TH_LURBU, MASK_TH_LURBU, match_opcode, 0}, +{"th.surd", 64, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xtu2@25", MATCH_TH_SURD, MASK_TH_SURD, match_opcode, 0}, +{"th.surw", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xtu2@25", MATCH_TH_SURW, MASK_TH_SURW, match_opcode, 0}, +{"th.surh", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xtu2@25", MATCH_TH_SURH, MASK_TH_SURH, match_opcode, 0}, +{"th.surb", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xtu2@25", MATCH_TH_SURB, MASK_TH_SURB, match_opcode, 0}, /* Vendor-specific (T-Head) XTheadMemPair instructions. */ -{"th.ldd", 64, INSN_CLASS_XTHEADMEMPAIR, "d,t,(s),Xu2@25,Xl4", MATCH_TH_LDD, MASK_TH_LDD, match_th_load_pair, 0}, -{"th.lwd", 0, INSN_CLASS_XTHEADMEMPAIR, "d,t,(s),Xu2@25,Xl3", MATCH_TH_LWD, MASK_TH_LWD, match_th_load_pair, 0}, -{"th.lwud", 0, INSN_CLASS_XTHEADMEMPAIR, "d,t,(s),Xu2@25,Xl3", MATCH_TH_LWUD, MASK_TH_LWUD, match_th_load_pair, 0}, -{"th.sdd", 64, INSN_CLASS_XTHEADMEMPAIR, "d,t,(s),Xu2@25,Xl4", MATCH_TH_SDD, MASK_TH_SDD, match_opcode, 0}, -{"th.swd", 0, INSN_CLASS_XTHEADMEMPAIR, "d,t,(s),Xu2@25,Xl3", MATCH_TH_SWD, MASK_TH_SWD, match_opcode, 0}, +{"th.ldd", 64, INSN_CLASS_XTHEADMEMPAIR, "d,t,(s),Xtu2@25,Xtl4", MATCH_TH_LDD, MASK_TH_LDD, match_th_load_pair, 0}, +{"th.lwd", 0, INSN_CLASS_XTHEADMEMPAIR, "d,t,(s),Xtu2@25,Xtl3", MATCH_TH_LWD, MASK_TH_LWD, match_th_load_pair, 0}, +{"th.lwud", 0, INSN_CLASS_XTHEADMEMPAIR, "d,t,(s),Xtu2@25,Xtl3", MATCH_TH_LWUD, MASK_TH_LWUD, match_th_load_pair, 0}, +{"th.sdd", 64, INSN_CLASS_XTHEADMEMPAIR, "d,t,(s),Xtu2@25,Xtl4", MATCH_TH_SDD, MASK_TH_SDD, match_opcode, 0}, +{"th.swd", 0, INSN_CLASS_XTHEADMEMPAIR, "d,t,(s),Xtu2@25,Xtl3", MATCH_TH_SWD, MASK_TH_SWD, match_opcode, 0}, /* Vendor-specific (T-Head) XTheadMac instructions. */ {"th.mula", 0, INSN_CLASS_XTHEADMAC, "d,s,t", MATCH_TH_MULA, MASK_TH_MULA, match_opcode, 0},