From: lkcl <lkcl@web>
Date: Wed, 25 May 2022 11:36:11 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2100
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6ded9908f83210af149cb162ff31b77916c607c4;p=libreriscv.git

---

diff --git a/openpower/sv/int_fp_mv.mdwn b/openpower/sv/int_fp_mv.mdwn
index cfa6dbba4..9a43d6818 100644
--- a/openpower/sv/int_fp_mv.mdwn
+++ b/openpower/sv/int_fp_mv.mdwn
@@ -19,7 +19,8 @@ and floating-point, therefore fast conversion/data-movement instructions
 are needed.  Also given that initialisation of floats tends to take up
 considerable space (even to just load 0.0) the inclusion of two compact
 format float immediate instructions is up for consideration using 16-bit
-immediates. BF16 is one of the formats.
+immediates. BF16 is one of the formats: a second instruction allows a full
+accuracy FP32 to be constructed.
 
 Libre-SOC will be compliant with the
 **Scalar Floating-Point Subset** (SFFS) i.e. is not implementing VMX/VSX,
@@ -89,6 +90,11 @@ number of instructions to get Floating Point constants into registers.
 but if followed up by `fishmv` an additional 16 bits of accuracy in the
 mantissa may be achieved.
 
+*IBM may consider it worthwhile to extend these two instructions to
+v3.1 Prefixed (`pfmvis` and `pfishmv`). If so it is recommended that
+`pfmvis` load a full FP32 immediate and `pfishmv` extend the lower
+32-bits to construct a full FP64 immediate.*
+
 ## Load BF16 Immediate
 
 `fmvis FRT, FI`