From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 6 Apr 2019 02:43:11 +0000 (+0100)
Subject: d_valid need not be created if stage_ctl is set
X-Git-Tag: ls180-24jan2020~1325
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6e1ee40f48b2d53fb661ca4199485f3876ea390c;p=ieee754fpu.git

d_valid need not be created if stage_ctl is set
---

diff --git a/src/add/singlepipe.py b/src/add/singlepipe.py
index 0c198aa7..7f3abc21 100644
--- a/src/add/singlepipe.py
+++ b/src/add/singlepipe.py
@@ -223,7 +223,8 @@ class NextControl:
         self.o_valid = Signal(name="n_o_valid") # self out>>  next
         self.i_ready = Signal(name="n_i_ready") # self <<in   next
         self.o_data = None # XXX MUST BE ADDED BY USER
-        self.d_valid = Signal(reset=1) # INTERNAL (data valid)
+        if self.stage_ctl:
+            self.d_valid = Signal(reset=1) # INTERNAL (data valid)
 
     @property
     def i_ready_test(self):