From: Andrew Zonenberg <azonenberg@drawersteak.com>
Date: Sun, 24 Apr 2016 05:53:49 +0000 (-0700)
Subject: Renamed VOUT to OUT on GP_ACMP cell
X-Git-Tag: yosys-0.7~243^2~2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6e215f374dcd92e2c1bff8ad6114f3d3dc9b06f5;p=yosys.git

Renamed VOUT to OUT on GP_ACMP cell
---

diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v
index e6b5db750..586b7a9b8 100644
--- a/techlibs/greenpak4/cells_sim.v
+++ b/techlibs/greenpak4/cells_sim.v
@@ -13,7 +13,7 @@ module GP_4LUT(input IN0, IN1, IN2, IN3, output OUT);
 	assign OUT = INIT[{IN3, IN2, IN1, IN0}];
 endmodule
 
-module GP_ACMP(input wire PWREN, input wire VIN, input wire VREF, output reg VOUT = 0);
+module GP_ACMP(input wire PWREN, input wire VIN, input wire VREF, output reg OUT);
 
 	parameter BANDWIDTH = "HIGH";
 	parameter VIN_BUF_EN = 0;
@@ -21,6 +21,8 @@ module GP_ACMP(input wire PWREN, input wire VIN, input wire VREF, output reg VOU
 	parameter VIN_ISRC_EN = 0;
 	parameter HYSTERESIS = 0;
 	
+	initial OUT = 0;
+	
 	//cannot simulate mixed signal IP
 
 endmodule