From: Jason Ekstrand Date: Wed, 27 Feb 2019 22:08:20 +0000 (-0600) Subject: anv: Implement VK_EXT_descriptor_indexing X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6e230d7607f9b3e082d00859bd7725c4dc87e5cf;p=mesa.git anv: Implement VK_EXT_descriptor_indexing Now that everything is in place to do bindless for all resource types except input attachments and UBOs, VK_EXT_descriptor_indexing is "trivial". Reviewed-by: Lionel Landwerlin Reviewed-by: Caio Marcelo de Oliveira Filho --- diff --git a/docs/relnotes/19.1.0.html b/docs/relnotes/19.1.0.html index 36d6dbe27c3..e42fd5ab3bf 100644 --- a/docs/relnotes/19.1.0.html +++ b/docs/relnotes/19.1.0.html @@ -46,6 +46,7 @@ TBD.
  • GL_KHR_parallel_shader_compile on all drivers.
  • VK_EXT_buffer_device_address on Intel and RADV.
  • VK_NV_compute_shader_derivatives on Intel.
    • +
  • VK_EXT_descriptor_indexing on Intel.

    • Bug fixes

    diff --git a/src/intel/vulkan/anv_descriptor_set.c b/src/intel/vulkan/anv_descriptor_set.c index c8747caa060..1ad89185dd7 100644 --- a/src/intel/vulkan/anv_descriptor_set.c +++ b/src/intel/vulkan/anv_descriptor_set.c @@ -208,7 +208,12 @@ anv_descriptor_requires_bindless(const struct anv_physical_device *pdevice, if (pdevice->always_use_bindless) return anv_descriptor_supports_bindless(pdevice, binding, sampler); - return false; + static const VkDescriptorBindingFlagBitsEXT flags_requiring_bindless = + VK_DESCRIPTOR_BINDING_UPDATE_AFTER_BIND_BIT_EXT | + VK_DESCRIPTOR_BINDING_UPDATE_UNUSED_WHILE_PENDING_BIT_EXT | + VK_DESCRIPTOR_BINDING_PARTIALLY_BOUND_BIT_EXT; + + return (binding->flags & flags_requiring_bindless) != 0; } void anv_GetDescriptorSetLayoutSupport( diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c index e7793f1170f..e7c0212f2e9 100644 --- a/src/intel/vulkan/anv_device.c +++ b/src/intel/vulkan/anv_device.c @@ -1031,11 +1031,37 @@ void anv_GetPhysicalDeviceFeatures2( break; } + case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES_EXT: { + VkPhysicalDeviceDescriptorIndexingFeaturesEXT *features = + (VkPhysicalDeviceDescriptorIndexingFeaturesEXT *)ext; + features->shaderInputAttachmentArrayDynamicIndexing = false; + features->shaderUniformTexelBufferArrayDynamicIndexing = true; + features->shaderStorageTexelBufferArrayDynamicIndexing = true; + features->shaderUniformBufferArrayNonUniformIndexing = false; + features->shaderSampledImageArrayNonUniformIndexing = true; + features->shaderStorageBufferArrayNonUniformIndexing = true; + features->shaderStorageImageArrayNonUniformIndexing = true; + features->shaderInputAttachmentArrayNonUniformIndexing = false; + features->shaderUniformTexelBufferArrayNonUniformIndexing = true; + features->shaderStorageTexelBufferArrayNonUniformIndexing = true; + features->descriptorBindingUniformBufferUpdateAfterBind = false; + features->descriptorBindingSampledImageUpdateAfterBind = true; + features->descriptorBindingStorageImageUpdateAfterBind = true; + features->descriptorBindingStorageBufferUpdateAfterBind = true; + features->descriptorBindingUniformTexelBufferUpdateAfterBind = true; + features->descriptorBindingStorageTexelBufferUpdateAfterBind = true; + features->descriptorBindingUpdateUnusedWhilePending = true; + features->descriptorBindingPartiallyBound = true; + features->descriptorBindingVariableDescriptorCount = false; + features->runtimeDescriptorArray = true; + break; + } + case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_FEATURES_EXT: { VkPhysicalDeviceInlineUniformBlockFeaturesEXT *features = (VkPhysicalDeviceInlineUniformBlockFeaturesEXT *)ext; features->inlineUniformBlock = true; - features->descriptorBindingInlineUniformBlockUpdateAfterBind = false; + features->descriptorBindingInlineUniformBlockUpdateAfterBind = true; break; } @@ -1316,6 +1342,49 @@ void anv_GetPhysicalDeviceProperties2( break; } + case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES_EXT: { + VkPhysicalDeviceDescriptorIndexingPropertiesEXT *props = + (VkPhysicalDeviceDescriptorIndexingPropertiesEXT *)ext; + + /* It's a bit hard to exactly map our implementation to the limits + * described here. The bindless surface handle in the extended + * message descriptors is 20 bits and it's an index into the table of + * RENDER_SURFACE_STATE structs that starts at bindless surface base + * address. Given that most things consume two surface states per + * view (general/sampled for textures and write-only/read-write for + * images), we claim 2^19 things. + * + * For SSBOs, we just use A64 messages so there is no real limit + * there beyond the limit on the total size of a descriptor set. + */ + const unsigned max_bindless_views = 1 << 19; + + props->maxUpdateAfterBindDescriptorsInAllPools = max_bindless_views; + props->shaderUniformBufferArrayNonUniformIndexingNative = false; + props->shaderSampledImageArrayNonUniformIndexingNative = false; + props->shaderStorageBufferArrayNonUniformIndexingNative = true; + props->shaderStorageImageArrayNonUniformIndexingNative = false; + props->shaderInputAttachmentArrayNonUniformIndexingNative = false; + props->robustBufferAccessUpdateAfterBind = true; + props->quadDivergentImplicitLod = false; + props->maxPerStageDescriptorUpdateAfterBindSamplers = max_bindless_views; + props->maxPerStageDescriptorUpdateAfterBindUniformBuffers = 0; + props->maxPerStageDescriptorUpdateAfterBindStorageBuffers = UINT32_MAX; + props->maxPerStageDescriptorUpdateAfterBindSampledImages = max_bindless_views; + props->maxPerStageDescriptorUpdateAfterBindStorageImages = max_bindless_views; + props->maxPerStageDescriptorUpdateAfterBindInputAttachments = 0; + props->maxPerStageUpdateAfterBindResources = UINT32_MAX; + props->maxDescriptorSetUpdateAfterBindSamplers = max_bindless_views; + props->maxDescriptorSetUpdateAfterBindUniformBuffers = 0; + props->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic = 0; + props->maxDescriptorSetUpdateAfterBindStorageBuffers = UINT32_MAX; + props->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic = MAX_DYNAMIC_BUFFERS / 2; + props->maxDescriptorSetUpdateAfterBindSampledImages = max_bindless_views; + props->maxDescriptorSetUpdateAfterBindStorageImages = max_bindless_views; + props->maxDescriptorSetUpdateAfterBindInputAttachments = 0; + break; + } + case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DRIVER_PROPERTIES_KHR: { VkPhysicalDeviceDriverPropertiesKHR *driver_props = (VkPhysicalDeviceDriverPropertiesKHR *) ext; diff --git a/src/intel/vulkan/anv_extensions.py b/src/intel/vulkan/anv_extensions.py index d937e4e4524..afd327eb4a5 100644 --- a/src/intel/vulkan/anv_extensions.py +++ b/src/intel/vulkan/anv_extensions.py @@ -122,6 +122,8 @@ EXTENSIONS = [ Extension('VK_EXT_conditional_rendering', 1, 'device->info.gen >= 8 || device->info.is_haswell'), Extension('VK_EXT_debug_report', 8, True), Extension('VK_EXT_depth_clip_enable', 1, True), + Extension('VK_EXT_descriptor_indexing', 2, + 'device->has_a64_buffer_access && device->has_bindless_images'), Extension('VK_EXT_direct_mode_display', 1, 'VK_USE_PLATFORM_DISPLAY_KHR'), Extension('VK_EXT_display_control', 1, 'VK_USE_PLATFORM_DISPLAY_KHR'), Extension('VK_EXT_display_surface_counter', 1, 'VK_USE_PLATFORM_DISPLAY_KHR'), diff --git a/src/intel/vulkan/anv_nir_apply_pipeline_layout.c b/src/intel/vulkan/anv_nir_apply_pipeline_layout.c index 846964b04e7..23b1cb72098 100644 --- a/src/intel/vulkan/anv_nir_apply_pipeline_layout.c +++ b/src/intel/vulkan/anv_nir_apply_pipeline_layout.c @@ -268,6 +268,12 @@ try_lower_direct_buffer_intrinsic(nir_intrinsic_instr *intrin, bool is_atomic, if (is_atomic && nir_dest_bit_size(intrin->dest) == 64) return false; + /* Normal binding table-based messages can't handle non-uniform access so + * we have to fall back to A64. + */ + if (nir_intrinsic_access(intrin) & ACCESS_NON_UNIFORM) + return false; + if (!nir_deref_find_descriptor(deref, state)) return false; diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c index 09abf4e85fd..64d4d93803c 100644 --- a/src/intel/vulkan/anv_pipeline.c +++ b/src/intel/vulkan/anv_pipeline.c @@ -138,6 +138,7 @@ anv_shader_compile_to_nir(struct anv_device *device, .lower_workgroup_access_to_offsets = true, .caps = { .derivative_group = true, + .descriptor_array_dynamic_indexing = true, .device_group = true, .draw_parameters = true, .float16 = pdevice->info.gen >= 8, @@ -152,6 +153,7 @@ anv_shader_compile_to_nir(struct anv_device *device, .multiview = true, .physical_storage_buffer_address = pdevice->has_a64_buffer_access, .post_depth_coverage = pdevice->info.gen >= 9, + .runtime_descriptor_array = true, .shader_viewport_index_layer = true, .stencil_export = pdevice->info.gen >= 9, .storage_8bit = pdevice->info.gen >= 8, @@ -638,6 +640,13 @@ anv_pipeline_lower_nir(struct anv_pipeline *pipeline, ssbo_address_format); NIR_PASS_V(nir, nir_opt_constant_folding); + + /* We don't support non-uniform UBOs and non-uniform SSBO access is + * handled naturally by falling back to A64 messages. + */ + NIR_PASS_V(nir, nir_lower_non_uniform_access, + nir_lower_non_uniform_texture_access | + nir_lower_non_uniform_image_access); } if (nir->info.stage != MESA_SHADER_COMPUTE)