From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 2 Aug 2019 00:49:55 +0000 (+0100)
Subject: update test
X-Git-Tag: ls180-24jan2020~566
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6e24978ae2f6e3dcf337e6b66de46f01a0ae3a7e;p=ieee754fpu.git

update test
---

diff --git a/src/nmutil/test/test_buf_pipe.py b/src/nmutil/test/test_buf_pipe.py
index 9035d932..e27f382b 100644
--- a/src/nmutil/test/test_buf_pipe.py
+++ b/src/nmutil/test/test_buf_pipe.py
@@ -19,13 +19,15 @@ from nmigen.hdl.rec import Record
 from nmigen.compat.sim import run_simulation
 from nmigen.cli import verilog, rtlil
 
-from .example_buf_pipe import ExampleBufPipe, ExampleBufPipeAdd
-from .example_buf_pipe import ExamplePipeline, UnbufferedPipeline
-from .example_buf_pipe import ExampleStageCls
-from .example_buf_pipe import PrevControl, NextControl, BufferedHandshake
-from .example_buf_pipe import StageChain, ControlBase, StageCls
+from nmutil.test.example_buf_pipe import ExampleBufPipe, ExampleBufPipeAdd
+from nmutil.test.example_buf_pipe import ExamplePipeline, UnbufferedPipeline
+from nmutil.test.example_buf_pipe import ExampleStageCls
+from nmutil.iocontrol import PrevControl, NextControl
+from nmutil.stageapi import StageChain, StageCls
+from nmutil.singlepipe import ControlBase
 from nmutil.singlepipe import UnbufferedPipeline2
 from nmutil.singlepipe import SimpleHandshake
+from nmutil.singlepipe import BufferedHandshake
 from nmutil.singlepipe import PassThroughHandshake
 from nmutil.singlepipe import PassThroughStage
 from nmutil.singlepipe import FIFOControl