From: Tsukasa OI Date: Mon, 24 Jul 2023 05:09:39 +0000 (+0000) Subject: RISC-V: Implications from 'Zc[fd]' extensions X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6e30678feb8ab38ad80a589226c5d0e9c9dc399e;p=binutils-gdb.git RISC-V: Implications from 'Zc[fd]' extensions The version 1.0.4-1 of the code size reduction specification clarifies that 'Zcf' implies 'F' and 'Zcd' implies 'D'. cf: This commit adds those implications. bfd/ChangeLog: * elfxx-riscv.c (riscv_implicit_subsets): Add two implications, 'Zcf' -> 'F' and 'Zcd' -> 'D'. gas/ChangeLog: * testsuite/gas/riscv/march-imply-zcd.d: New test. * testsuite/gas/riscv/march-imply-zcf.d: New test. --- diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index eaf496649db..b43d2cfa0fa 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1132,6 +1132,8 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = {"zvl256b", "zvl128b", check_implicit_always}, {"zvl128b", "zvl64b", check_implicit_always}, {"zvl64b", "zvl32b", check_implicit_always}, + {"zcd", "d", check_implicit_always}, + {"zcf", "f", check_implicit_always}, {"zfa", "f", check_implicit_always}, {"d", "f", check_implicit_always}, {"zfh", "zfhmin", check_implicit_always}, diff --git a/gas/testsuite/gas/riscv/march-imply-zcd.d b/gas/testsuite/gas/riscv/march-imply-zcd.d new file mode 100644 index 00000000000..e7c75f649a8 --- /dev/null +++ b/gas/testsuite/gas/riscv/march-imply-zcd.d @@ -0,0 +1,6 @@ +#as: -march=rv32i_zcd -march-attr -misa-spec=20191213 +#readelf: -A +#source: empty.s +Attribute Section: riscv +File Attributes + Tag_RISCV_arch: "rv32i2p1_f2p2_d2p2_zicsr2p0_zca1p0_zcd1p0" diff --git a/gas/testsuite/gas/riscv/march-imply-zcf.d b/gas/testsuite/gas/riscv/march-imply-zcf.d new file mode 100644 index 00000000000..3829637a16f --- /dev/null +++ b/gas/testsuite/gas/riscv/march-imply-zcf.d @@ -0,0 +1,6 @@ +#as: -march=rv32i_zcf -march-attr -misa-spec=20191213 +#readelf: -A +#source: empty.s +Attribute Section: riscv +File Attributes + Tag_RISCV_arch: "rv32i2p1_f2p2_zicsr2p0_zca1p0_zcf1p0"