From: Sebastien Bourdeauducq <sebastien@milkymist.org>
Date: Sun, 24 Nov 2013 22:42:31 +0000 (+0100)
Subject: platforms/papilio_pro: fix clock signal handling
X-Git-Tag: 24jan2021_ls180~2099^2~437
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6e48682a5e735e17e71d6e617acb5f8b11359163;p=litex.git

platforms/papilio_pro: fix clock signal handling
---

diff --git a/mibuild/platforms/papilio_pro.py b/mibuild/platforms/papilio_pro.py
index 7c8a6316..47fed774 100644
--- a/mibuild/platforms/papilio_pro.py
+++ b/mibuild/platforms/papilio_pro.py
@@ -41,4 +41,13 @@ _io = [
 class Platform(XilinxISEPlatform):
 	def __init__(self):
 		XilinxISEPlatform.__init__(self, "xc6slx9-tqg144-2", _io,
-			lambda p: CRG_SE(p, "clk32", None, 31.25))
+			lambda p: CRG_SE(p, "clk32", None))
+
+	def do_finalize(self, fragment):
+		try:
+			self.add_platform_command("""
+NET "{clk32}" TNM_NET = "GRPclk32";
+TIMESPEC "TSclk32" = PERIOD "GRPclk32" 31.25 ns HIGH 50%;
+""", clk32=self.lookup_request("clk32"))
+		except ConstraintError:
+			pass