From: Florent Kermarrec Date: Sat, 21 Mar 2015 11:55:39 +0000 (+0100) Subject: sdram: split sdram_timing in sdram_timing_settings/sdram_controller_settings X-Git-Tag: 24jan2021_ls180~2468 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6e4b7c6cfd435b2ac7d9bb63773409616bc6e6c3;p=litex.git sdram: split sdram_timing in sdram_timing_settings/sdram_controller_settings req_queue_size, read_time, write_time settings are not sdram_timing settings but sdram controller settings --- diff --git a/misoclib/mem/sdram/__init__.py b/misoclib/mem/sdram/__init__.py index f861d63c..00acf678 100644 --- a/misoclib/mem/sdram/__init__.py +++ b/misoclib/mem/sdram/__init__.py @@ -8,5 +8,6 @@ GeomSettingsT = namedtuple("_GeomSettings", "bank_a row_a col_a mux_a") def GeomSettings(bank_a, row_a, col_a): return GeomSettingsT(bank_a, row_a, col_a, max(row_a, col_a)) -TimingSettings = namedtuple("TimingSettings", "tRP tRCD tWR tWTR tREFI tRFC" \ - " req_queue_size read_time write_time") +TimingSettings = namedtuple("TimingSettings", "tRP tRCD tWR tWTR tREFI tRFC") + +ControllerSettings = namedtuple("ControllerSettings", "req_queue_size read_time write_time") diff --git a/misoclib/mem/sdram/core/__init__.py b/misoclib/mem/sdram/core/__init__.py index f3127752..b0114947 100644 --- a/misoclib/mem/sdram/core/__init__.py +++ b/misoclib/mem/sdram/core/__init__.py @@ -7,22 +7,23 @@ from misoclib.mem.sdram.core import minicon, lasmicon from misoclib.mem.sdram.core import lasmixbar class SDRAMCore(Module, AutoCSR): - def __init__(self, phy, ramcon_type, sdram_geom, sdram_timing, **kwargs): + def __init__(self, phy, ramcon_type, geom_settings, timing_settings, controller_settings, **kwargs): # DFI - self.submodules.dfii = dfii.DFIInjector(sdram_geom.mux_a, sdram_geom.bank_a, + self.submodules.dfii = dfii.DFIInjector(geom_settings.mux_a, geom_settings.bank_a, phy.settings.dfi_d, phy.settings.nphases) self.comb += Record.connect(self.dfii.master, phy.dfi) # LASMICON if ramcon_type == "lasmicon": - self.submodules.controller = controller = lasmicon.LASMIcon(phy.settings, sdram_geom, sdram_timing, **kwargs) + self.submodules.controller = controller = lasmicon.LASMIcon(phy.settings, geom_settings, timing_settings, + controller_settings, **kwargs) self.comb += Record.connect(controller.dfi, self.dfii.slave) self.submodules.crossbar = crossbar = lasmixbar.LASMIxbar([controller.lasmic], controller.nrowbits) # MINICON elif ramcon_type == "minicon": - self.submodules.controller = controller = minicon.Minicon(phy.settings, sdram_geom, sdram_timing) + self.submodules.controller = controller = minicon.Minicon(phy.settings, geom_settings, timing_settings) self.comb += Record.connect(controller.dfi, self.dfii.slave) else: raise ValueError("Unsupported SDRAM controller type: {}".format(self.ramcon_type)) diff --git a/misoclib/mem/sdram/core/lasmicon/__init__.py b/misoclib/mem/sdram/core/lasmicon/__init__.py index 393e218b..5d213dd1 100644 --- a/misoclib/mem/sdram/core/lasmicon/__init__.py +++ b/misoclib/mem/sdram/core/lasmicon/__init__.py @@ -7,7 +7,7 @@ from misoclib.mem.sdram.core.lasmicon.bankmachine import * from misoclib.mem.sdram.core.lasmicon.multiplexer import * class LASMIcon(Module): - def __init__(self, phy_settings, geom_settings, timing_settings, **kwargs): + def __init__(self, phy_settings, geom_settings, timing_settings, controller_settings, **kwargs): if phy_settings.memtype in ["SDR"]: burst_length = phy_settings.nphases*1 # command multiplication*SDR elif phy_settings.memtype in ["DDR", "LPDDR", "DDR2", "DDR3"]: @@ -22,7 +22,7 @@ class LASMIcon(Module): aw=geom_settings.row_a + geom_settings.col_a - address_align, dw=phy_settings.dfi_d*phy_settings.nphases, nbanks=2**geom_settings.bank_a, - req_queue_size=timing_settings.req_queue_size, + req_queue_size=controller_settings.req_queue_size, read_latency=phy_settings.read_latency+1, write_latency=phy_settings.write_latency+1) self.nrowbits = geom_settings.col_a - address_align @@ -31,10 +31,10 @@ class LASMIcon(Module): self.submodules.refresher = Refresher(geom_settings.mux_a, geom_settings.bank_a, timing_settings.tRP, timing_settings.tREFI, timing_settings.tRFC) - self.submodules.bank_machines = [BankMachine(geom_settings, timing_settings, address_align, i, + self.submodules.bank_machines = [BankMachine(geom_settings, timing_settings, controller_settings, address_align, i, getattr(self.lasmic, "bank"+str(i))) for i in range(2**geom_settings.bank_a)] - self.submodules.multiplexer = Multiplexer(phy_settings, geom_settings, timing_settings, + self.submodules.multiplexer = Multiplexer(phy_settings, geom_settings, timing_settings, controller_settings, self.bank_machines, self.refresher, self.dfi, self.lasmic, **kwargs) diff --git a/misoclib/mem/sdram/core/lasmicon/bankmachine.py b/misoclib/mem/sdram/core/lasmicon/bankmachine.py index 3397bb36..bb1d9c76 100644 --- a/misoclib/mem/sdram/core/lasmicon/bankmachine.py +++ b/misoclib/mem/sdram/core/lasmicon/bankmachine.py @@ -26,7 +26,7 @@ class _AddressSlicer: return Cat(Replicate(0, self.address_align), address[:split]) class BankMachine(Module): - def __init__(self, geom_settings, timing_settings, address_align, bankn, req): + def __init__(self, geom_settings, timing_settings, controller_settings, address_align, bankn, req): self.refresh_req = Signal() self.refresh_gnt = Signal() self.cmd = CommandRequestRW(geom_settings.mux_a, geom_settings.bank_a) @@ -34,7 +34,7 @@ class BankMachine(Module): ### # Request FIFO - self.submodules.req_fifo = SyncFIFO([("we", 1), ("adr", flen(req.adr))], timing_settings.req_queue_size) + self.submodules.req_fifo = SyncFIFO([("we", 1), ("adr", flen(req.adr))], controller_settings.req_queue_size) self.comb += [ self.req_fifo.din.we.eq(req.we), self.req_fifo.din.adr.eq(req.adr), diff --git a/misoclib/mem/sdram/core/lasmicon/multiplexer.py b/misoclib/mem/sdram/core/lasmicon/multiplexer.py index fe47e7c9..db24e633 100644 --- a/misoclib/mem/sdram/core/lasmicon/multiplexer.py +++ b/misoclib/mem/sdram/core/lasmicon/multiplexer.py @@ -89,7 +89,7 @@ class _Steerer(Module): ] class Multiplexer(Module, AutoCSR): - def __init__(self, phy_settings, geom_settings, timing_settings, bank_machines, refresher, dfi, lasmic, + def __init__(self, phy_settings, geom_settings, timing_settings, controller_settings, bank_machines, refresher, dfi, lasmic, with_bandwidth=False): assert(phy_settings.nphases == len(dfi.phases)) @@ -137,8 +137,8 @@ class Multiplexer(Module, AutoCSR): else: self.comb += max_time.eq(0) return en, max_time - read_time_en, max_read_time = anti_starvation(timing_settings.read_time) - write_time_en, max_write_time = anti_starvation(timing_settings.write_time) + read_time_en, max_read_time = anti_starvation(controller_settings.read_time) + write_time_en, max_write_time = anti_starvation(controller_settings.write_time) # Refresh self.comb += [bm.refresh_req.eq(refresher.req) for bm in bank_machines] diff --git a/misoclib/soc/sdram.py b/misoclib/soc/sdram.py index 237cad22..82725b65 100644 --- a/misoclib/soc/sdram.py +++ b/misoclib/soc/sdram.py @@ -32,7 +32,7 @@ class SDRAMSoC(SoC): self._sdram_phy_registered = False - def register_sdram_phy(self, phy, sdram_geom, sdram_timing): + def register_sdram_phy(self, phy, geom_settings, timing_settings, controller_settings): if self._sdram_phy_registered: raise FinalizeError self._sdram_phy_registered = True @@ -40,7 +40,7 @@ class SDRAMSoC(SoC): raise NotImplementedError("Minicon only supports SDR memtype for now (" + phy.settings.memtype + ")") # Core - self.submodules.sdram = SDRAMCore(phy, self.ramcon_type, sdram_geom, sdram_timing) + self.submodules.sdram = SDRAMCore(phy, self.ramcon_type, geom_settings, timing_settings, controller_settings) # LASMICON frontend if self.ramcon_type == "lasmicon": @@ -68,7 +68,7 @@ class SDRAMSoC(SoC): # MINICON frontend elif self.ramcon_type == "minicon": sdram_width = flen(self.sdram.controller.bus.dat_r) - main_ram_size = 2**(sdram_geom.bank_a+sdram_geom.row_a+sdram_geom.col_a)*sdram_width//8 + main_ram_size = 2**(geom_settings.bank_a+geom_settings.row_a+geom_settings.col_a)*sdram_width//8 if sdram_width == 32: self.register_mem("sdram", self.mem_map["sdram"], self.sdram.controller.bus, main_ram_size) diff --git a/targets/de0nano.py b/targets/de0nano.py index 769613ea..c1be8d68 100644 --- a/targets/de0nano.py +++ b/targets/de0nano.py @@ -90,26 +90,27 @@ class BaseSoC(SDRAMSoC): self.submodules.crg = _CRG(platform) if not self.with_main_ram: - sdram_geom = sdram.GeomSettings( + sdram_geom_settings = sdram.GeomSettings( bank_a=2, row_a=13, col_a=9 ) - sdram_timing = sdram.TimingSettings( + sdram_timing_settings = sdram.TimingSettings( tRP=self.ns(20), tRCD=self.ns(20), tWR=self.ns(20), tWTR=2, tREFI=self.ns(7800, False), - tRFC=self.ns(70), - + tRFC=self.ns(70) + ) + sdram_controller_settings = sdram.ControllerSettings( req_queue_size=8, read_time=32, write_time=16 ) - self.submodules.sdrphy = gensdrphy.GENSDRPHY(platform.request("sdram")) - self.register_sdram_phy(self.sdrphy, sdram_geom, sdram_timing) + self.register_sdram_phy(self.sdrphy, sdram_geom_settings, sdram_timing_settings, + sdram_controller_settings) default_subtarget = BaseSoC diff --git a/targets/kc705.py b/targets/kc705.py index 75079483..0006e500 100644 --- a/targets/kc705.py +++ b/targets/kc705.py @@ -83,25 +83,27 @@ class BaseSoC(SDRAMSoC): self.submodules.crg = _CRG(platform) if not self.with_main_ram: - sdram_geom = sdram.GeomSettings( + sdram_geom_settings = sdram.GeomSettings( bank_a=3, row_a=16, col_a=10 ) - sdram_timing = sdram.TimingSettings( + sdram_timing_settings = sdram.TimingSettings( tRP=self.ns(15), tRCD=self.ns(15), tWR=self.ns(15), tWTR=2, tREFI=self.ns(7800, False), - tRFC=self.ns(70), - + tRFC=self.ns(70) + ) + sdram_controller_settings = sdram.ControllerSettings( req_queue_size=8, read_time=32, write_time=16 ) self.submodules.ddrphy = k7ddrphy.K7DDRPHY(platform.request("ddram"), memtype="DDR3") - self.register_sdram_phy(self.ddrphy, sdram_geom, sdram_timing) + self.register_sdram_phy(self.ddrphy, sdram_geom_settings, sdram_timing_settings, + sdram_controller_settings) spiflash_pads = platform.request("spiflash") spiflash_pads.clk = Signal() diff --git a/targets/mlabs_video.py b/targets/mlabs_video.py index 0278b342..54943497 100644 --- a/targets/mlabs_video.py +++ b/targets/mlabs_video.py @@ -41,26 +41,28 @@ class BaseSoC(SDRAMSoC): self.submodules.crg = mxcrg.MXCRG(_MXClockPads(platform), self.clk_freq) if not self.with_main_ram: - sdram_geom = sdram.GeomSettings( + sdram_geom_settings = sdram.GeomSettings( bank_a=2, row_a=13, col_a=10 ) - sdram_timing = sdram.TimingSettings( + sdram_timing_settings = sdram.TimingSettings( tRP=self.ns(15), tRCD=self.ns(15), tWR=self.ns(15), tWTR=2, tREFI=self.ns(7800, False), tRFC=self.ns(70), - + ) + sdram_controller_settings = sdram.ControllerSettings( req_queue_size=8, read_time=32, write_time=16 ) self.submodules.ddrphy = s6ddrphy.S6DDRPHY(platform.request("ddram"), memtype="DDR", rd_bitslip=0, wr_bitslip=3, dqs_ddr_alignment="C1") - self.register_sdram_phy(self.ddrphy, sdram_geom, sdram_timing) + self.register_sdram_phy(self.ddrphy, sdram_geom_settings, sdram_timing_settings, + sdram_controller_settings) self.comb += [ diff --git a/targets/pipistrello.py b/targets/pipistrello.py index 3bab29a4..57b4f9c1 100644 --- a/targets/pipistrello.py +++ b/targets/pipistrello.py @@ -98,18 +98,20 @@ class BaseSoC(SDRAMSoC): self.submodules.crg = _CRG(platform, clk_freq) if not self.with_main_ram: - sdram_geom = sdram.GeomSettings( + sdram_geom_settings = sdram.GeomSettings( bank_a=2, row_a=13, col_a=10 ) - sdram_timing = sdram.TimingSettings( + sdram_timing_settings = sdram.TimingSettings( tRP=self.ns(15), tRCD=self.ns(15), tWR=self.ns(15), tWTR=2, tREFI=self.ns(64*1000*1000/8192, False), - tRFC=self.ns(72), + tRFC=self.ns(72) + ) + sdram_controller_settings = sdram.ControllerSettings( req_queue_size=8, read_time=32, write_time=16 @@ -123,7 +125,8 @@ class BaseSoC(SDRAMSoC): platform.add_platform_command(""" PIN "BUFG.O" CLOCK_DEDICATED_ROUTE = FALSE; """) - self.register_sdram_phy(self.ddrphy, sdram_geom, sdram_timing) + self.register_sdram_phy(self.ddrphy, sdram_geom_settings, sdram_timing_settings, + sdram_controller_settings) self.submodules.spiflash = spiflash.SpiFlash(platform.request("spiflash4x"), dummy=10, div=4) # If not in ROM, BIOS is in SPI flash diff --git a/targets/ppro.py b/targets/ppro.py index c50e9bb4..ffd83195 100644 --- a/targets/ppro.py +++ b/targets/ppro.py @@ -74,24 +74,27 @@ class BaseSoC(SDRAMSoC): self.submodules.crg = _CRG(platform, clk_freq) if not self.with_main_ram: - sdram_geom = sdram.GeomSettings( + sdram_geom_settings = sdram.GeomSettings( bank_a=2, row_a=12, col_a=8 ) - sdram_timing = sdram.TimingSettings( + sdram_timing_settings = sdram.TimingSettings( tRP=self.ns(15), tRCD=self.ns(15), tWR=self.ns(14), tWTR=2, tREFI=self.ns(64*1000*1000/4096, False), - tRFC=self.ns(66), + tRFC=self.ns(66) + ) + sdram_controller_settings = sdram.ControllerSettings( req_queue_size=8, read_time=32, write_time=16 ) self.submodules.sdrphy = gensdrphy.GENSDRPHY(platform.request("sdram")) - self.register_sdram_phy(self.sdrphy, sdram_geom, sdram_timing) + self.register_sdram_phy(self.sdrphy, sdram_geom_settings, sdram_timing_settings, + sdram_controller_settings) self.submodules.spiflash = spiflash.SpiFlash(platform.request("spiflash2x"), dummy=4, div=6) self.flash_boot_address = 0x70000