From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 8 Jul 2021 18:02:37 +0000 (+0100)
Subject: add ability to explicitly increment SVSTATE srcstep/dststep
X-Git-Tag: xlen-bcd~326
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6e4efa1c66ee1a2fc84c56625ddff7ed7dd0818b;p=openpower-isa.git

add ability to explicitly increment SVSTATE srcstep/dststep
---

diff --git a/openpower/isa/simplev.mdwn b/openpower/isa/simplev.mdwn
index a5182547..97e6aff2 100644
--- a/openpower/isa/simplev.mdwn
+++ b/openpower/isa/simplev.mdwn
@@ -12,7 +12,7 @@ SVL-Form
 Pseudo-code:
 
     if (vf & (¬vs) & ¬(ms)) = 1 then
-        SVSTATE_NEXT(vf)
+        SVSTATE_NEXT
     else
         VLimm <- SVi + 1
         if vs = 1 then
@@ -30,7 +30,8 @@ Pseudo-code:
             VL = MVL
         SVSTATE[0:6] <- MVL
         SVSTATE[7:13] <- VL
-        RT <- [0]*57 || VL
+        if _RT != 0b00000 then
+            GPR(_RT) <- [0]*57 || VL
         MSR[6] <- vf
 
 Special Registers Altered:
diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index aeefe257..600e0827 100644
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -107,11 +107,20 @@ class GPR(dict):
             self[i] = SelectableInt(regfile[i], 64)
 
     def __call__(self, ridx):
+        if isinstance(ridx, SelectableInt):
+            ridx = ridx.value
         return self[ridx]
 
     def set_form(self, form):
         self.form = form
 
+    def __setitem__(self, rnum, value):
+        # rnum = rnum.value # only SelectableInt allowed
+        log("GPR setitem", rnum, value)
+        if isinstance(rnum, SelectableInt):
+            rnum = rnum.value
+        dict.__setitem__(self, rnum, value)
+
     def getz(self, rnum):
         # rnum = rnum.value # only SelectableInt allowed
         log("GPR getzero?", rnum)
@@ -479,7 +488,8 @@ def get_pdecode_idx_out(dec2, name):
             return out, o_isvec
     elif name == 'RT':
         log ("get_pdecode_idx_out", out_sel, OutSel.RT.value,
-                                      OutSel.RT_OR_ZERO.value, out, o_isvec)
+                                      OutSel.RT_OR_ZERO.value, out, o_isvec,
+                                      dec2.dec.RT)
         if out_sel == OutSel.RT.value:
             return out, o_isvec
     elif name == 'FRA':
@@ -1115,81 +1125,19 @@ class ISACaller:
             dest_cr, src_cr, src_byname, dest_byname = False, False, {}, {}
         log ("sv rm", sv_rm, dest_cr, src_cr, src_byname, dest_byname)
 
-        # get SVSTATE VL (oh and print out some debug stuff)
-        if self.is_svp64_mode:
-            vl = self.svstate.vl.asint(msb0=True)
-            srcstep = self.svstate.srcstep.asint(msb0=True)
-            dststep = self.svstate.dststep.asint(msb0=True)
-            sv_a_nz = yield self.dec2.sv_a_nz
-            fft_mode = yield self.dec2.use_svp64_fft
-            in1 = yield self.dec2.e.read_reg1.data
-            log ("SVP64: VL, srcstep, dststep, sv_a_nz, in1 fft",
-                    vl, srcstep, dststep, sv_a_nz, in1, fft_mode)
-
-        # get predicate mask
-        srcmask = dstmask = 0xffff_ffff_ffff_ffff
+        # see if srcstep/dststep need skipping over masked-out predicate bits
         if self.is_svp64_mode:
-            pmode = yield self.dec2.rm_dec.predmode
-            reverse_gear = yield self.dec2.rm_dec.reverse_gear
-            sv_ptype = yield self.dec2.dec.op.SV_Ptype
-            srcpred = yield self.dec2.rm_dec.srcpred
-            dstpred = yield self.dec2.rm_dec.dstpred
-            pred_src_zero = yield self.dec2.rm_dec.pred_sz
-            pred_dst_zero = yield self.dec2.rm_dec.pred_dz
-            if pmode == SVP64PredMode.INT.value:
-                srcmask = dstmask = get_predint(self.gpr, dstpred)
-                if sv_ptype == SVPtype.P2.value:
-                    srcmask = get_predint(self.gpr, srcpred)
-            elif pmode == SVP64PredMode.CR.value:
-                srcmask = dstmask = get_predcr(self.crl, dstpred, vl)
-                if sv_ptype == SVPtype.P2.value:
-                    srcmask = get_predcr(self.crl, srcpred, vl)
-            log ("    pmode", pmode)
-            log ("    reverse", reverse_gear)
-            log ("    ptype", sv_ptype)
-            log ("    srcpred", bin(srcpred))
-            log ("    dstpred", bin(dstpred))
-            log ("    srcmask", bin(srcmask))
-            log ("    dstmask", bin(dstmask))
-            log ("    pred_sz", bin(pred_src_zero))
-            log ("    pred_dz", bin(pred_dst_zero))
-
-            # okaaay, so here we simply advance srcstep (TODO dststep)
-            # until the predicate mask has a "1" bit... or we run out of VL
-            # let srcstep==VL be the indicator to move to next instruction
-            if not pred_src_zero:
-                while (((1<<srcstep) & srcmask) == 0) and (srcstep != vl):
-                    log ("      skip", bin(1<<srcstep))
-                    srcstep += 1
-            # same for dststep
-            if not pred_dst_zero:
-                while (((1<<dststep) & dstmask) == 0) and (dststep != vl):
-                    log ("      skip", bin(1<<dststep))
-                    dststep += 1
-
-            # now work out if the relevant mask bits require zeroing
-            if pred_dst_zero:
-                pred_dst_zero = ((1<<dststep) & dstmask) == 0
-            if pred_src_zero:
-                pred_src_zero = ((1<<srcstep) & srcmask) == 0
-
-            # update SVSTATE with new srcstep
-            self.svstate.srcstep[0:7] = srcstep
-            self.svstate.dststep[0:7] = dststep
-            self.namespace['SVSTATE'] = self.svstate.spr
-            yield self.dec2.state.svstate.eq(self.svstate.spr.value)
-            yield Settle() # let decoder update
-            srcstep = self.svstate.srcstep.asint(msb0=True)
-            dststep = self.svstate.dststep.asint(msb0=True)
-            log ("    srcstep", srcstep)
-            log ("    dststep", dststep)
-
-            # check if end reached (we let srcstep overrun, above)
-            # nothing needs doing (TODO zeroing): just do next instruction
-            if srcstep == vl or dststep == vl:
+            self.update_new_svstate_steps()
+            pre = yield from self.svstate_pre_inc()
+            if pre:
                 self.svp64_reset_loop()
+                self.update_nia()
                 self.update_pc_next()
                 return
+            srcstep, dststep = self.new_srcstep, self.new_dststep
+            vl = self.svstate.vl.asint(msb0=True)
+            pred_src_zero = yield self.dec2.rm_dec.pred_sz
+            pred_dst_zero = yield self.dec2.rm_dec.pred_dz
 
         # VL=0 in SVP64 mode means "do nothing: skip instruction"
         if self.is_svp64_mode and vl == 0:
@@ -1290,12 +1238,17 @@ class ISACaller:
                 log('reading reg %s %s' % (name, str(regnum)), is_vec)
                 if name in fregs:
                     reg_val = self.fpr(regnum)
-                else:
+                elif name is not None:
                     reg_val = self.gpr(regnum)
             else:
                 log('zero input reg %s %s' % (name, str(regnum)), is_vec)
                 reg_val = 0
             inputs.append(reg_val)
+        # arrrrgh, awful hack, to get _RT into namespace
+        if asmop == 'setvl':
+            regname = "_RT"
+            RT = yield self.dec2.dec.RT
+            self.namespace[regname] = SelectableInt(RT, 5)
 
         # in SVP64 mode for LD/ST work out immediate
         # XXX TODO: replace_ds for DS-Form rather than D-Form.
@@ -1478,44 +1431,11 @@ class ISACaller:
         # check if it is the SVSTATE.src/dest step that needs incrementing
         # this is our Sub-Program-Counter loop from 0 to VL-1
         if self.is_svp64_mode:
-            # XXX twin predication TODO
-            vl = self.svstate.vl.asint(msb0=True)
-            mvl = self.svstate.maxvl.asint(msb0=True)
-            srcstep = self.svstate.srcstep.asint(msb0=True)
-            dststep = self.svstate.dststep.asint(msb0=True)
-            rm_mode = yield self.dec2.rm_dec.mode
-            reverse_gear = yield self.dec2.rm_dec.reverse_gear
-            sv_ptype = yield self.dec2.dec.op.SV_Ptype
-            out_vec = not (yield self.dec2.no_out_vec)
-            in_vec = not (yield self.dec2.no_in_vec)
-            log ("    svstate.vl", vl)
-            log ("    svstate.mvl", mvl)
-            log ("    svstate.srcstep", srcstep)
-            log ("    svstate.dststep", dststep)
-            log ("    mode", rm_mode)
-            log ("    reverse", reverse_gear)
-            log ("    out_vec", out_vec)
-            log ("    in_vec", in_vec)
-            log ("    sv_ptype", sv_ptype, sv_ptype == SVPtype.P2.value)
-            # check if srcstep needs incrementing by one, stop PC advancing
-            # svp64 loop can end early if the dest is scalar for single-pred
-            # but for 2-pred both src/dest have to be checked.
-            # XXX this might not be true! it may just be LD/ST
-            if sv_ptype == SVPtype.P2.value:
-                svp64_is_vector = (out_vec or in_vec)
-            else:
-                svp64_is_vector = out_vec
-            if svp64_is_vector and srcstep != vl-1 and dststep != vl-1:
-                self.svstate.srcstep += SelectableInt(1, 7)
-                self.svstate.dststep += SelectableInt(1, 7)
-                self.pc.NIA.value = self.pc.CIA.value
-                self.namespace['NIA'] = self.pc.NIA
-                self.namespace['SVSTATE'] = self.svstate.spr
-                log("end of sub-pc call", self.namespace['CIA'],
-                                     self.namespace['NIA'])
-                return # DO NOT allow PC to update whilst Sub-PC loop running
-            # reset loop to zero
-            self.svp64_reset_loop()
+            post = yield from self.svstate_post_inc()
+            if post:
+                # reset loop to zero
+                self.svp64_reset_loop()
+                self.update_nia()
 
         # XXX only in non-SVP64 mode!
         # record state of whether the current operation was an svshape,
@@ -1526,6 +1446,136 @@ class ISACaller:
 
         self.update_pc_next()
 
+    def SVSTATE_NEXT(self):
+        """explicitly moves srcstep/dststep on to next element, for
+        "Vertical-First" mode.  this function is called from
+        setvl pseudo-code, as a pseudo-op "svstep"
+        """
+        log("SVSTATE_NEXT")
+        self.allow_next_step_inc = True
+
+    def svstate_pre_inc(self):
+        """check if srcstep/dststep need to skip over masked-out predicate bits
+        """
+        # get SVSTATE VL (oh and print out some debug stuff)
+        vl = self.svstate.vl.asint(msb0=True)
+        srcstep = self.svstate.srcstep.asint(msb0=True)
+        dststep = self.svstate.dststep.asint(msb0=True)
+        sv_a_nz = yield self.dec2.sv_a_nz
+        fft_mode = yield self.dec2.use_svp64_fft
+        in1 = yield self.dec2.e.read_reg1.data
+        log ("SVP64: VL, srcstep, dststep, sv_a_nz, in1 fft",
+                vl, srcstep, dststep, sv_a_nz, in1, fft_mode)
+
+        # get predicate mask
+        srcmask = dstmask = 0xffff_ffff_ffff_ffff
+
+        pmode = yield self.dec2.rm_dec.predmode
+        reverse_gear = yield self.dec2.rm_dec.reverse_gear
+        sv_ptype = yield self.dec2.dec.op.SV_Ptype
+        srcpred = yield self.dec2.rm_dec.srcpred
+        dstpred = yield self.dec2.rm_dec.dstpred
+        pred_src_zero = yield self.dec2.rm_dec.pred_sz
+        pred_dst_zero = yield self.dec2.rm_dec.pred_dz
+        if pmode == SVP64PredMode.INT.value:
+            srcmask = dstmask = get_predint(self.gpr, dstpred)
+            if sv_ptype == SVPtype.P2.value:
+                srcmask = get_predint(self.gpr, srcpred)
+        elif pmode == SVP64PredMode.CR.value:
+            srcmask = dstmask = get_predcr(self.crl, dstpred, vl)
+            if sv_ptype == SVPtype.P2.value:
+                srcmask = get_predcr(self.crl, srcpred, vl)
+        log ("    pmode", pmode)
+        log ("    reverse", reverse_gear)
+        log ("    ptype", sv_ptype)
+        log ("    srcpred", bin(srcpred))
+        log ("    dstpred", bin(dstpred))
+        log ("    srcmask", bin(srcmask))
+        log ("    dstmask", bin(dstmask))
+        log ("    pred_sz", bin(pred_src_zero))
+        log ("    pred_dz", bin(pred_dst_zero))
+
+        # okaaay, so here we simply advance srcstep (TODO dststep)
+        # until the predicate mask has a "1" bit... or we run out of VL
+        # let srcstep==VL be the indicator to move to next instruction
+        if not pred_src_zero:
+            while (((1<<srcstep) & srcmask) == 0) and (srcstep != vl):
+                log ("      skip", bin(1<<srcstep))
+                srcstep += 1
+        # same for dststep
+        if not pred_dst_zero:
+            while (((1<<dststep) & dstmask) == 0) and (dststep != vl):
+                log ("      skip", bin(1<<dststep))
+                dststep += 1
+
+        # now work out if the relevant mask bits require zeroing
+        if pred_dst_zero:
+            pred_dst_zero = ((1<<dststep) & dstmask) == 0
+        if pred_src_zero:
+            pred_src_zero = ((1<<srcstep) & srcmask) == 0
+
+        # store new srcstep / dststep
+        self.new_srcstep, self.new_dststep = srcstep, dststep
+
+    def update_new_svstate_steps(self):
+        srcstep, dststep = self.new_srcstep, self.new_dststep
+
+        # update SVSTATE with new srcstep
+        self.svstate.srcstep[0:7] = srcstep
+        self.svstate.dststep[0:7] = dststep
+        self.namespace['SVSTATE'] = self.svstate.spr
+        yield self.dec2.state.svstate.eq(self.svstate.spr.value)
+        yield Settle() # let decoder update
+        srcstep = self.svstate.srcstep.asint(msb0=True)
+        dststep = self.svstate.dststep.asint(msb0=True)
+        log ("    srcstep", srcstep)
+        log ("    dststep", dststep)
+
+        # check if end reached (we let srcstep overrun, above)
+        # nothing needs doing (TODO zeroing): just do next instruction
+        return srcstep == vl or dststep == vl
+
+    def svstate_post_inc(self):
+        # check if it is the SVSTATE.src/dest step that needs incrementing
+        # this is our Sub-Program-Counter loop from 0 to VL-1
+        # XXX twin predication TODO
+        vl = self.svstate.vl.asint(msb0=True)
+        mvl = self.svstate.maxvl.asint(msb0=True)
+        srcstep = self.svstate.srcstep.asint(msb0=True)
+        dststep = self.svstate.dststep.asint(msb0=True)
+        rm_mode = yield self.dec2.rm_dec.mode
+        reverse_gear = yield self.dec2.rm_dec.reverse_gear
+        sv_ptype = yield self.dec2.dec.op.SV_Ptype
+        out_vec = not (yield self.dec2.no_out_vec)
+        in_vec = not (yield self.dec2.no_in_vec)
+        log ("    svstate.vl", vl)
+        log ("    svstate.mvl", mvl)
+        log ("    svstate.srcstep", srcstep)
+        log ("    svstate.dststep", dststep)
+        log ("    mode", rm_mode)
+        log ("    reverse", reverse_gear)
+        log ("    out_vec", out_vec)
+        log ("    in_vec", in_vec)
+        log ("    sv_ptype", sv_ptype, sv_ptype == SVPtype.P2.value)
+        # check if srcstep needs incrementing by one, stop PC advancing
+        # svp64 loop can end early if the dest is scalar for single-pred
+        # but for 2-pred both src/dest have to be checked.
+        # XXX this might not be true! it may just be LD/ST
+        if sv_ptype == SVPtype.P2.value:
+            svp64_is_vector = (out_vec or in_vec)
+        else:
+            svp64_is_vector = out_vec
+        if svp64_is_vector and srcstep != vl-1 and dststep != vl-1:
+            self.svstate.srcstep += SelectableInt(1, 7)
+            self.svstate.dststep += SelectableInt(1, 7)
+            self.pc.NIA.value = self.pc.CIA.value
+            self.namespace['NIA'] = self.pc.NIA
+            self.namespace['SVSTATE'] = self.svstate.spr
+            log("end of sub-pc call", self.namespace['CIA'],
+                                 self.namespace['NIA'])
+            return False # DO NOT allow PC update whilst Sub-PC loop running
+        return True
+
     def update_pc_next(self):
         # UPDATE program counter
         self.pc.update(self.namespace, self.is_svp64_mode)
@@ -1538,10 +1588,11 @@ class ISACaller:
         self.svstate.srcstep[0:7] = 0
         self.svstate.dststep[0:7] = 0
         log ("    svstate.srcstep loop end (PC to update)")
-        self.pc.update_nia(self.is_svp64_mode)
-        self.namespace['NIA'] = self.pc.NIA
         self.namespace['SVSTATE'] = self.svstate.spr
 
+    def update_nia(self):
+        self.pc.update_nia(self.is_svp64_mode)
+        self.namespace['NIA'] = self.pc.NIA
 
 def inject():
     """Decorator factory.
diff --git a/src/openpower/decoder/isa/test_caller_setvl.py b/src/openpower/decoder/isa/test_caller_setvl.py
index b6cdc6ed..9093ba6f 100644
--- a/src/openpower/decoder/isa/test_caller_setvl.py
+++ b/src/openpower/decoder/isa/test_caller_setvl.py
@@ -21,7 +21,32 @@ class DecoderTestCase(FHDLTestCase):
         for i in range(32):
             self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64))
 
-    def test_setvl_1(self):
+    def tst_svstep_1(self):
+        lst = SVP64Asm(["setvl 0, 0, 9, 1, 1, 1",
+                        "setvl 0, 0, 0, 1, 0, 0"
+                        ])
+        lst = list(lst)
+
+        # SVSTATE (in this case, VL=2)
+        svstate = SVP64State()
+        svstate.vl[0:7] = 2 # VL
+        svstate.maxvl[0:7] = 2 # MAXVL
+        print ("SVSTATE", bin(svstate.spr.asint()))
+
+        with Program(lst, bigendian=False) as program:
+            sim = self.run_tst_program(program, svstate=svstate)
+            print ("SVSTATE after", bin(sim.svstate.spr.asint()))
+            print ("        vl", bin(sim.svstate.vl.asint(True)))
+            print ("        mvl", bin(sim.svstate.maxvl.asint(True)))
+            print ("    srcstep", bin(sim.svstate.srcstep.asint(True)))
+            print ("    dststep", bin(sim.svstate.dststep.asint(True)))
+            self.assertEqual(sim.svstate.vl.asint(True), 10)
+            self.assertEqual(sim.svstate.maxvl.asint(True), 10)
+            self.assertEqual(sim.svstate.maxvl.asint(True), 10)
+            print("      gpr1", sim.gpr(0))
+            self.assertEqual(sim.gpr(0), SelectableInt(0, 64))
+
+    def tst_setvl_1(self):
         lst = SVP64Asm(["setvl 1, 0, 9, 0, 1, 1",
                         ])
         lst = list(lst)
diff --git a/src/openpower/decoder/pseudo/parser.py b/src/openpower/decoder/pseudo/parser.py
index 6b11359c..e32d25a3 100644
--- a/src/openpower/decoder/pseudo/parser.py
+++ b/src/openpower/decoder/pseudo/parser.py
@@ -393,10 +393,11 @@ class PowerParser:
                       | expr_stmt"""
         if isinstance(p[1], ast.Call):
             p[0] = ast.Expr(p[1])
-        elif isinstance(p[1], ast.Name) and p[1].id == 'TRAP':
-            # TRAP needs to actually be a function
+        elif isinstance(p[1], ast.Name) and p[1].id in ['TRAP', 'SVSTATE_NEXT']:
+            fname = p[1].id
+            # TRAP and SVSTATE_NEXT needs to actually be a function
             name = ast.Name("self", ast.Load())
-            name = ast.Attribute(name, "TRAP", ast.Load())
+            name = ast.Attribute(name, fname, ast.Load())
             p[0] = ast.Call(name, [], [])
         else:
             p[0] = p[1]