From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 24 Mar 2022 22:13:13 +0000 (+0000)
Subject: increase delay on ECP5 ulx3s
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6e4f5d6d66865ef3a5feb83a310f568d907c160f;p=ls2.git

increase delay on ECP5 ulx3s
---

diff --git a/src/crg.py b/src/crg.py
index 1141b26..af2ccb1 100644
--- a/src/crg.py
+++ b/src/crg.py
@@ -206,7 +206,7 @@ class ECPIX5CRG(Elaboratable):
         m.submodules.pll = pll = PLL(ClockSignal("rawclk"), reset=~reset)
 
         # Power-on delay (655us)
-        podcnt = Signal(18, reset=-1)
+        podcnt = Signal(23, reset=-1)
         pod_done = Signal()
         with m.If((podcnt != 0) & pll.locked):
             m.d.rawclk += podcnt.eq(podcnt-1)
diff --git a/src/ls2.py b/src/ls2.py
index e4a7188..e458989 100644
--- a/src/ls2.py
+++ b/src/ls2.py
@@ -589,7 +589,7 @@ def build_platform(fpga, firmware):
     if fpga == 'arty_a7':
         clk_freq = 50e6
     if fpga == 'ulx3s':
-        clk_freq = 12.5e6
+        clk_freq = 25.0e6
 
     # select a firmware address
     fw_addr = None