From: Ben Widawsky Date: Thu, 19 Feb 2015 23:49:34 +0000 (-0800) Subject: i965/skl: Use 1 register for uniform pull constant payload X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6e62a52865787362ae1deb9dee80140d3a66c519;p=mesa.git i965/skl: Use 1 register for uniform pull constant payload When under dispatch_width=16 the previous code would allocate 2 registers for the payload when only one is needed. This manifested itself through bugs on SKL which needs to mess with this instruction. Ken though this might impact shader-db, but apparently it doesn't Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89118 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88999 Signed-off-by: Ben Widawsky Reviewed-by: Kenneth Graunke Tested-by: Timo Aaltonen --- diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp index a2a5234b0e9..9e1676e628c 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp @@ -3063,7 +3063,7 @@ fs_visitor::lower_uniform_pull_constant_loads() assert(const_offset_reg.file == IMM && const_offset_reg.type == BRW_REGISTER_TYPE_UD); const_offset_reg.fixed_hw_reg.dw1.ud /= 4; - fs_reg payload = vgrf(glsl_type::uint_type); + fs_reg payload = fs_reg(GRF, alloc.allocate(1)); /* We have to use a message header on Skylake to get SIMD4x2 mode. * Reserve space for the register.