From: lkcl <lkcl@web>
Date: Thu, 4 Jul 2019 16:41:40 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~4306
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6e65499c0dff056024569250421d16d549f7970b;p=libreriscv.git

---

diff --git a/simple_v_extension/vblock_format.mdwn b/simple_v_extension/vblock_format.mdwn
index 832e0c393..cf5c0f9e8 100644
--- a/simple_v_extension/vblock_format.mdwn
+++ b/simple_v_extension/vblock_format.mdwn
@@ -2,7 +2,7 @@
 
 * Copyright (C) 2017, 2018, 2019 Luke Kenneth Casson Leighton
 * Status: DRAFTv0.6
-* Last edited: 29 jun 2019
+* Last edited: 5 jul 2019
 
 [[!toc ]]
 
@@ -51,6 +51,14 @@ in a single instruction.
 
 # VBLOCK Prefix
 
+The purpose of the VBLOCK Prefix is to specify the context in which a block of RV Scalar instructions are "vectorised" and/or predicated.
+
+As there are not very many bits available without going into a prefix format longer than 16 bits, some abbreviations are used. Two bits are dedicated to specifying whether the Register and Predicate formats are 16 or 8 bit.
+
+Also, the number of entries in each table is specified with an unusual encoding, on the basis that if registers are to be Vectorised, it is highly likely that they will be predicated as well.
+
+The format is explained as follows:
+
 * Bit 7 specifies if the register prefix block format is the full 16 bit format
   (1) or the compact less expressive format (0).
 * 8 bit format predicate numbering is implicit and begins from x9. Thus