From: lkcl <lkcl@web>
Date: Thu, 20 Oct 2022 22:12:07 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~62
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6e6902d0bfa700ccab5d640cb55d6867eff52547;p=libreriscv.git

---

diff --git a/openpower/sv/rfc/ls003.mdwn b/openpower/sv/rfc/ls003.mdwn
index 2e3158ff4..1f49463ff 100644
--- a/openpower/sv/rfc/ls003.mdwn
+++ b/openpower/sv/rfc/ls003.mdwn
@@ -69,8 +69,10 @@ allowing highly-efficient arbitrary-length big-integer division.
 
 **Notes and Observations**:
 
-1. There is no need for an Rc=1 variant as VA-Form is being used.
-2. There is no need for Special Registers as VA-Form is being used. 
+1. It is not practical to add Rc=1 variants as VA-Form is used and
+   there is a **pair** of results produced.
+2. An overflow variant (XER.OV set) of `divmod2du` would be valuable
+   but VA-Form EXT004 is under severe pressure. 
 3. Both instructions have been present in Intel x86 for several decades.
 4. Neither instruction is present in VSX: these are 128/64 whereas
    VSX is 128/128.