From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 12 Jul 2020 21:08:45 +0000 (+0100)
Subject: attempting to get test_trap_sim working, seems to switch mode
X-Git-Tag: div_pipeline~72
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6e78d390faf2b5a48a4f4b1cbf7ac0c859f6fc23;p=soc.git

attempting to get test_trap_sim working, seems to switch mode
---

diff --git a/src/soc/simulator/qemu.py b/src/soc/simulator/qemu.py
index 747e4a94..41ef1690 100644
--- a/src/soc/simulator/qemu.py
+++ b/src/soc/simulator/qemu.py
@@ -11,6 +11,11 @@ launch_args_le = ['qemu-system-ppc64le',
                '-nographic',
                '-s', '-S']
 
+def swap_order(x, nbytes):
+    x = x.to_bytes(nbytes, byteorder='little')
+    x = int.from_bytes(x, byteorder='big', signed=False)
+    return x
+
 
 class QemuController:
     def __init__(self, kernel, bigendian):
@@ -22,6 +27,7 @@ class QemuController:
                                            stdout=subprocess.PIPE,
                                            stdin=subprocess.PIPE)
         self.gdb = GdbController(gdb_path='powerpc64-linux-gnu-gdb')
+        self.bigendian = bigendian
 
     def __enter__(self):
         return self
@@ -79,7 +85,9 @@ class QemuController:
         for x in res:
             if(x["type"]=="result"):
                 assert 'register-values' in x['payload']
-                return int(x['payload']['register-values'][0]['value'], 0)
+                res = int(x['payload']['register-values'][0]['value'], 0)
+                return res
+                #return swap_order(res, 8)
         return None
 
     # TODO: use -data-list-register-names instead of hardcoding the values
diff --git a/src/soc/simulator/test_trap_sim.py b/src/soc/simulator/test_trap_sim.py
index b69561e3..dfb4faa2 100644
--- a/src/soc/simulator/test_trap_sim.py
+++ b/src/soc/simulator/test_trap_sim.py
@@ -14,7 +14,7 @@ from soc.simulator.qemu import run_program
 from soc.decoder.isa.all import ISA
 from soc.fu.test.common import TestCase
 from soc.simulator.test_sim import DecoderBase
-
+from soc.config.endian import bigendian
 
 
 class TrapSimTestCases(FHDLTestCase):
@@ -28,14 +28,14 @@ class TrapSimTestCases(FHDLTestCase):
         lst = ["addi 1, 0, 0x5678",
                "twi  4, 1, 0x5677",
                ]
-        with Program(lst) as program:
+        with Program(lst, bigendian) as program:
             self.run_tst_program(program, [1])
 
     def test_1_twi_eq(self):
         lst = ["addi 1, 0, 0x5678",
                "twi  4, 1, 0x5678",
                ]
-        with Program(lst) as program:
+        with Program(lst, bigendian) as program:
             self.run_tst_program(program, [1])
 
     def run_tst_program(self, prog, initial_regs=None, initial_sprs=None,