From: Kevin Lim <ktlim@umich.edu>
Date: Thu, 22 Jun 2006 22:09:31 +0000 (-0400)
Subject: Misc fixes.
X-Git-Tag: m5_2.0_beta1~36^2~51
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6e95bcd333784e1292293980cb2c2fba9f2ac467;p=gem5.git

Misc fixes.

src/cpu/o3/alpha_dyn_inst_impl.hh:
    Consolidate these calls into one.
src/cpu/o3/commit_impl.hh:
    Include checker only if it's being used.
src/cpu/o3/fetch_impl.hh:
    Do not deallocate request if it's a squashed response that was received.
src/cpu/o3/lsq_unit.hh:
    Add in comment.
src/cpu/o3/lsq_unit_impl.hh:
    Only include checker if it's being used.

--HG--
extra : convert_revision : aae0bf1e19baae90f1e61d41191548612bbb3be6
---

diff --git a/src/cpu/o3/alpha_dyn_inst_impl.hh b/src/cpu/o3/alpha_dyn_inst_impl.hh
index 6183a755e..855ee9963 100644
--- a/src/cpu/o3/alpha_dyn_inst_impl.hh
+++ b/src/cpu/o3/alpha_dyn_inst_impl.hh
@@ -102,15 +102,7 @@ template <class Impl>
 Fault
 AlphaDynInst<Impl>::completeAcc(Packet *pkt)
 {
-    if (this->isLoad()) {
-        this->fault = this->staticInst->completeAcc(pkt, this,
-                                                    this->traceData);
-    } else if (this->isStore()) {
-        this->fault = this->staticInst->completeAcc(pkt, this,
-                                                    this->traceData);
-    } else {
-        panic("Unknown type!");
-    }
+    this->fault = this->staticInst->completeAcc(pkt, this, this->traceData);
 
     return this->fault;
 }
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index 566324b69..176f83246 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -36,11 +36,14 @@
 
 #include "base/loader/symtab.hh"
 #include "base/timebuf.hh"
-#include "cpu/checker/cpu.hh"
 #include "cpu/exetrace.hh"
 #include "cpu/o3/commit.hh"
 #include "cpu/o3/thread_state.hh"
 
+#if USE_CHECKER
+#include "cpu/checker/cpu.hh"
+#endif
+
 using namespace std;
 
 template <class Impl>
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index 7cbf0ab02..e570dbb18 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -357,7 +357,6 @@ DefaultFetch<Impl>::processCacheCompletion(PacketPtr pkt)
         ++fetchIcacheSquashes;
         delete pkt->req;
         delete pkt;
-        memReq[tid] = NULL;
         return;
     }
 
diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh
index cef6e0a2e..9b67e61f2 100644
--- a/src/cpu/o3/lsq_unit.hh
+++ b/src/cpu/o3/lsq_unit.hh
@@ -128,6 +128,8 @@ class LSQUnit {
     /** Writes back stores. */
     void writebackStores();
 
+    /** Completes the data access that has been returned from the
+     * memory system. */
     void completeDataAccess(PacketPtr pkt);
 
     /** Clears all the entries in the LQ. */
diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
index f4a656aa1..714acb2ef 100644
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -31,12 +31,15 @@
 
 #include "config/use_checker.hh"
 
-#include "cpu/checker/cpu.hh"
 #include "cpu/o3/lsq_unit.hh"
 #include "base/str.hh"
 #include "mem/packet.hh"
 #include "mem/request.hh"
 
+#if USE_CHECKER
+#include "cpu/checker/cpu.hh"
+#endif
+
 template<class Impl>
 LSQUnit<Impl>::WritebackEvent::WritebackEvent(DynInstPtr &_inst, PacketPtr _pkt,
                                               LSQUnit *lsq_ptr)