From: Dmitry Selyutin <ghostmansd@gmail.com>
Date: Sun, 18 Sep 2022 18:37:44 +0000 (+0300)
Subject: power_insn: fix coding style
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6ea7f24875ef5188dfac7e92c83128a34bb82c90;p=openpower-isa.git

power_insn: fix coding style
---

diff --git a/src/openpower/decoder/power_insn.py b/src/openpower/decoder/power_insn.py
index c6e27cab..05c64856 100644
--- a/src/openpower/decoder/power_insn.py
+++ b/src/openpower/decoder/power_insn.py
@@ -1800,12 +1800,13 @@ class RM(BaseRM):
 
         elif record.svp64.mode is _SVMode.BRANCH:
             # just mode 5-bit. could be reduced down to 2, oh well.
-            #         mode       mask   action(getattr)
-            table = [(0b00000, 0b11000, "simple"), # simple
-                     (0b01000, 0b11000, "vls"),    # VLset
-                     (0b10000, 0b11000, "ctr"),    # CTR mode
-                     (0b11000, 0b11000, "ctrvls"), # CTR+VLset mode
-                    ]
+            #    mode     mask     member
+            table = (
+                (0b00000, 0b11000, "simple"), # simple
+                (0b01000, 0b11000, "vls"),    # VLset
+                (0b10000, 0b11000, "ctr"),    # CTR mode
+                (0b11000, 0b11000, "ctrvls"), # CTR+VLset mode
+            )
             # slightly weird: doesn't have a 5-bit "mode" field like others
             search = int(rm[19:23])