From: Doug Evans <dje@google.com>
Date: Wed, 20 May 1998 07:54:31 +0000 (+0000)
Subject: 	Zero bottom two bits of pc in jmp,jl insns.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6ebf4a955926365907f00b459402050ea7bfe5f9;p=binutils-gdb.git

	Zero bottom two bits of pc in jmp,jl insns.
	* sem.c,sem-switch.c: Regenerate.
	* semx.c: Regenerate.
---

diff --git a/sim/m32r/ChangeLog b/sim/m32r/ChangeLog
index d5eaba5d208..8f44ace24ac 100644
--- a/sim/m32r/ChangeLog
+++ b/sim/m32r/ChangeLog
@@ -1,3 +1,11 @@
+Wed May 20 00:10:40 1998  Doug Evans  <devans@seba.cygnus.com>
+
+	Zero bottom two bits of pc in jmp,jl insns.
+	* sem.c,sem-switch.c: Regenerate.
+start-sanitize-m32rx
+	* semx.c: Regenerate.
+end-sanitize-m32rx
+
 Tue May 19 16:45:33 1998  Doug Evans  <devans@seba.cygnus.com>
 
 	* sim-if.c (do_trap): Treat traps 2-15 as hardware does.
diff --git a/sim/m32r/semx.c b/sim/m32r/semx.c
index 941937cb897..a16ddac07a7 100644
--- a/sim/m32r/semx.c
+++ b/sim/m32r/semx.c
@@ -1502,7 +1502,7 @@ SEM_FN_NAME (m32rx,jl) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec
 do {
   SI temp1;SI temp0;
   temp0 = ADDSI (ANDSI (OPRND (pc), -4), 4);
-  temp1 = OPRND (sr);
+  temp1 = ANDSI (OPRND (sr), -4);
   CPU (h_gr[14]) = temp0;
   TRACE_RESULT (current_cpu, "gr-14", 'x', CPU (h_gr[14]));
   BRANCH_NEW_PC (new_pc, SEM_BRANCH_VIA_ADDR (sem_arg, temp1));
@@ -1538,7 +1538,7 @@ SEM_FN_NAME (m32rx,jmp) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exe
   EXTRACT_FMT_JMP_VARS /* f-op1 f-r1 f-op2 f-r2 */
   EXTRACT_FMT_JMP_CODE
 
-  BRANCH_NEW_PC (new_pc, SEM_BRANCH_VIA_ADDR (sem_arg, OPRND (sr)));
+  BRANCH_NEW_PC (new_pc, SEM_BRANCH_VIA_ADDR (sem_arg, ANDSI (OPRND (sr), -4)));
   taken_p = 1;
   TRACE_RESULT (current_cpu, "pc", 'x', new_pc);