From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 13 Nov 2020 16:04:15 +0000 (+0000)
Subject: rename ls180 litex pll_48 output to pll_18
X-Git-Tag: 24jan2021_ls180~100
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6ec3d32ed28acca2d301512876d3ae6f7b45ad78;p=soc.git

rename ls180 litex pll_48 output to pll_18
---

diff --git a/libreriscv b/libreriscv
index 0dbab7b5..6c32e647 160000
--- a/libreriscv
+++ b/libreriscv
@@ -1 +1 @@
-Subproject commit 0dbab7b582bdcf7e75aadff81551abec621d81f2
+Subproject commit 6c32e64727c7030a7c672620b281b4f3a9076ffd
diff --git a/pinmux b/pinmux
index 8145bb58..7f8cbf72 160000
--- a/pinmux
+++ b/pinmux
@@ -1 +1 @@
-Subproject commit 8145bb58bc29bd642e6c9a3653b942783e6a3e87
+Subproject commit 7f8cbf72abced671b4d0d1ae358d656470220ca4
diff --git a/src/soc/litex/florent/libresoc/core.py b/src/soc/litex/florent/libresoc/core.py
index 370f9cdc..b01c5fc8 100644
--- a/src/soc/litex/florent/libresoc/core.py
+++ b/src/soc/litex/florent/libresoc/core.py
@@ -239,10 +239,10 @@ class LibreSoC(CPU):
 
         # add clock select, pll output
         if variant == "ls180":
-            self.pll_48_o = Signal()
+            self.pll_18_o = Signal()
             self.clk_sel = Signal(3)
             self.cpu_params['i_clk_sel_i'] = self.clk_sel
-            self.cpu_params['o_pll_48_o'] = self.pll_48_o
+            self.cpu_params['o_pll_18_o'] = self.pll_18_o
 
         # add wishbone buses to cpu params
         self.cpu_params.update(make_wb_bus("ibus", ibus))
diff --git a/src/soc/litex/florent/libresoc/ls180.py b/src/soc/litex/florent/libresoc/ls180.py
index c47cbea5..f8580d37 100644
--- a/src/soc/litex/florent/libresoc/ls180.py
+++ b/src/soc/litex/florent/libresoc/ls180.py
@@ -50,7 +50,7 @@ def io():
         ("sys_clk", 0, Pins("G2"), IOStandard("LVCMOS33")),
         ("sys_rst",   0, Pins("R1"), IOStandard("LVCMOS33")),
         ("sys_clksel_i",   0, Pins("R1 R2 R3"), IOStandard("LVCMOS33")),
-        ("sys_pll_48_o",   0, Pins("R1"), IOStandard("LVCMOS33")),
+        ("sys_pll_18_o",   0, Pins("R1"), IOStandard("LVCMOS33")),
 
         # JTAG0: 4 pins
         ("jtag", 0,
diff --git a/src/soc/litex/florent/ls180soc.py b/src/soc/litex/florent/ls180soc.py
index 4279effc..52c83ea4 100755
--- a/src/soc/litex/florent/ls180soc.py
+++ b/src/soc/litex/florent/ls180soc.py
@@ -365,10 +365,10 @@ class LibreSoCSim(SoCCore):
 
         # PLL/Clock Select
         clksel_i = platform.request("sys_clksel_i")
-        pll48_o = platform.request("sys_pll_48_o")
+        pll18_o = platform.request("sys_pll_18_o")
 
         self.comb += self.cpu.clk_sel.eq(clksel_i) # allow clock src select
-        self.comb += pll48_o.eq(self.cpu.pll_48_o) # "test feed" from the PLL
+        self.comb += pll18_o.eq(self.cpu.pll_18_o) # "test feed" from the PLL
 
         #ram_init = []