From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 21 Jun 2019 18:45:53 +0000 (-0700)
Subject: Add more muxpack tests, with overlapping entries
X-Git-Tag: yosys-0.9~48^2~6
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6ec816098153c733b97410ebc6aef166db8affd8;p=yosys.git

Add more muxpack tests, with overlapping entries
---

diff --git a/tests/various/muxpack.v b/tests/various/muxpack.v
index 3a1086dbf..7a658d754 100644
--- a/tests/various/muxpack.v
+++ b/tests/various/muxpack.v
@@ -187,7 +187,9 @@ module case_nonexclusive_select (
 );
         always @* begin
             case (x)
-                0, 2: o = b;
+                //0, 2: o = b;
+                0: o = b;
+                2: o = b;
                 1: o = c;
                 default: begin
                     o = a;
@@ -197,3 +199,54 @@ module case_nonexclusive_select (
         endcase
         end
 endmodule
+
+module case_nonoverlap (
+        input wire [2:0] x,
+        input wire a, b, c, d, e, f, g,
+        output reg o
+);
+        always @* begin
+            case (x)
+                //0, 2: o = b; // Creates $reduce_or
+                //0: o = b; 2: o = b; // Creates $reduce_or
+                0: o = b;
+                2: o = f;
+                1: o = c;
+                default:
+                    case (x)
+                        //3, 4: o = d; // Creates $reduce_or
+                        //3: o = d; 4: o = d; // Creates $reduce_or
+                        3: o = d;
+                        4: o = g;
+                        5: o = e;
+                        default: o = 1'b0;
+                    endcase
+        endcase
+        end
+endmodule
+
+module case_overlap (
+        input wire [2:0] x,
+        input wire a, b, c, d, e, f, g,
+        output reg o
+);
+        always @* begin
+            case (x)
+                //0, 2: o = b; // Creates $reduce_or
+                //0: o = b; 2: o = b; // Creates $reduce_or
+                0: o = b;
+                2: o = f;
+                1: o = c;
+                default:
+                    case (x)
+                        //3, 4: o = d; // Creates $reduce_or
+                        //3: o = d; 4: o = d; // Creates $reduce_or
+                        2: o = 1'b1; // Overlaps with previous $pmux
+                        3: o = d;
+                        4: o = g;
+                        5: o = e;
+                        default: o = 1'b0;
+                    endcase
+        endcase
+        end
+endmodule
diff --git a/tests/various/muxpack.ys b/tests/various/muxpack.ys
index 579dad8d3..ef8a6dab9 100644
--- a/tests/various/muxpack.ys
+++ b/tests/various/muxpack.ys
@@ -212,3 +212,33 @@ design -import gold -as gold
 design -import gate -as gate
 miter -equiv -flatten -make_assert -make_outputs gold gate miter
 sat -verify -prove-asserts -show-ports miter
+
+design -load read
+hierarchy -top case_nonoverlap
+prep
+design -save gold
+muxpack
+opt
+stat
+select -assert-count 0 t:$mux
+select -assert-count 1 t:$pmux
+design -stash gate
+design -import gold -as gold
+design -import gate -as gate
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports miter
+
+design -load read
+hierarchy -top case_overlap
+prep
+design -save gold
+muxpack
+#opt # Do not opt otherwise $pmux's overlapping entry will get removed
+stat
+select -assert-count 0 t:$mux
+select -assert-count 1 t:$pmux
+design -stash gate
+design -import gold -as gold
+design -import gate -as gate
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports miter