From: lkcl <lkcl@web>
Date: Sun, 25 Sep 2022 12:56:40 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~283
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6eceded1744c8d7a58f6a414e095b6b2cb318dab;p=libreriscv.git

---

diff --git a/openpower/sv/cr_ops.mdwn b/openpower/sv/cr_ops.mdwn
index f737d800c..72e9d9ec7 100644
--- a/openpower/sv/cr_ops.mdwn
+++ b/openpower/sv/cr_ops.mdwn
@@ -81,7 +81,7 @@ SVP64 RM `MODE` (includes `ELWIDTH_SRC` bits) for CR-based operations:
 | / |SNZ| 0 RG  |   0 | dz  sz  | simple mode                      |
 | / |SNZ| 0 RG  |   1 | dz  sz   | scalar reduce mode (mapreduce) |
 |zz |SNZ| 1 VLI | inv |  CR-bit | Ffirst 3-bit mode      |
-| / |SNZ| 1 VLI | inv |  dz sz  | Ffirst 5-bit mode       |
+| / |SNZ| 1 VLI | inv |  dz sz  | Ffirst 5-bit mode (implies CR-bit=EQ) |
 
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