From: Frank Ch. Eigler Date: Mon, 30 Mar 1998 23:56:52 +0000 (+0000) Subject: * Continuing sky R5900 / COP2 work. Added extra sanitize tags to hide X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6ed00b060706ba0b2ef7cb68bd2d0275d846e99c;p=binutils-gdb.git * Continuing sky R5900 / COP2 work. Added extra sanitize tags to hide 128-bit MIPS part. [ChangeLog] Mon Mar 30 18:41:43 1998 Frank Ch. Eigler * interp.c (decode_coproc): Continuing COP2 work. (cop_[ls]q): Hide 128-bit COP2 more. * sim-main.h (COP_[LS]Q): Hide 128-bit COP2 more. [ChangeLog.sky] Mon Mar 30 18:44:15 1998 Frank Ch. Eigler * sky-libvpe.c: Code too wide - ran indent on SCEI code. * sky-vu.h (vu0_busy*, vu0_macro*): New entry points for COP2 interface. * sky-vu.c (vu0_busy*, vu0_macro*): Stub functions for above. --- diff --git a/sim/mips/ChangeLog b/sim/mips/ChangeLog index fcf834c0c27..a86e551f018 100644 --- a/sim/mips/ChangeLog +++ b/sim/mips/ChangeLog @@ -1,3 +1,12 @@ +start-sanitize-sky +Mon Mar 30 18:41:43 1998 Frank Ch. Eigler + + * interp.c (decode_coproc): Continuing COP2 work. + (cop_[ls]q): Hide 128-bit COP2 more. + + * sim-main.h (COP_[LS]Q): Hide 128-bit COP2 more. +end-sanitize-sky + Mon Mar 30 14:46:05 1998 Gavin Koch * configure.in (mipstx39*-*-*): Use gencode simulator rather @@ -30,13 +39,12 @@ start-sanitize-sky * sim-main.h (status_CU[012]): Added COP[n]-enabled flags for status register. -end-sanitize-sky - * interp.c (cop_lq, cop_sq): New functions for future 128-bit access to coprocessor registers. * sim-main.h (COP_LQ, COP_SQ): New macro front-ends for above. - +end-sanitize-sky + Fri Mar 27 16:15:52 1998 Andrew Cagney * configure: Regenerated to track ../common/aclocal.m4 changes. diff --git a/sim/mips/interp.c b/sim/mips/interp.c index cd8a8afaf53..6140938d977 100644 --- a/sim/mips/interp.c +++ b/sim/mips/interp.c @@ -3248,6 +3248,8 @@ cop_ld (SIM_DESC sd, } +/* start-sanitize-sky */ +#ifdef TARGET_SKY void cop_lq (SIM_DESC sd, sim_cpu *cpu, @@ -3258,11 +3260,9 @@ cop_lq (SIM_DESC sd, { switch (coproc_num) { - /* start-sanitize-sky */ case 2: /* XXX COP2 */ break; - /* end-sanitize-sky */ default: sim_io_printf(sd,"COP_LQ(%d,%d,??) at PC = 0x%s : TODO (architecture specific)\n", @@ -3272,6 +3272,8 @@ cop_lq (SIM_DESC sd, return; } +#endif /* TARGET_SKY */ +/* end-sanitize-sky */ unsigned int @@ -3334,6 +3336,8 @@ cop_sd (SIM_DESC sd, } +/* start-sanitize-sky */ +#ifdef TARGET_SKY unsigned128 cop_sq (SIM_DESC sd, sim_cpu *cpu, @@ -3341,14 +3345,12 @@ cop_sq (SIM_DESC sd, int coproc_num, int coproc_reg) { - unsigned128 value = {0, 0}; + unsigned128 value = U16_8(0, 0); switch (coproc_num) { - /* start-sanitize-sky */ case 2: /* XXX COP2 */ break; - /* end-sanitize-sky */ default: sim_io_printf(sd,"COP_SQ(%d,%d) at PC = 0x%s : TODO (architecture specific)\n", @@ -3358,6 +3360,8 @@ cop_sq (SIM_DESC sd, return(value); } +#endif /* TARGET_SKY */ +/* end-sanitize-sky */ void @@ -3513,9 +3517,9 @@ decode_coproc (SIM_DESC sd, int i_15_11 = (instruction >> 11) & 0x1f; int i_15_0 = instruction & 0xffff; int i_10_1 = (instruction >> 1) & 0x3ff; + int i_5_0 = instruction & 0x03f; int interlock = instruction & 0x01; - unsigned_4 vpe_status = sim_core_read_aligned_4 (cpu, cia, read_map, VPE0_STAT); - int vpe_busy = (vpe_status & 0x00000001); + int co = (instruction >> 25) & 0x01; /* setup for semantic.c-like actions below */ typedef unsigned_4 instruction_word; int CIA = cia; @@ -3535,91 +3539,128 @@ decode_coproc (SIM_DESC sd, if(i_25_21 == 0x08 && i_20_16 == 0x00) /* BC2F */ { address_word offset = EXTEND16(i_15_0) << 2; - if(! vpe_busy) DELAY_SLOT(cia + 4 + offset); + if(! vu0_busy()) DELAY_SLOT(cia + 4 + offset); } else if(i_25_21 == 0x08 && i_20_16==0x02) /* BC2FL */ { address_word offset = EXTEND16(i_15_0) << 2; - if(! vpe_busy) DELAY_SLOT(cia + 4 + offset); + if(! vu0_busy()) DELAY_SLOT(cia + 4 + offset); else NULLIFY_NEXT_INSTRUCTION(); } else if(i_25_21 == 0x08 && i_20_16 == 0x01) /* BC2T */ { address_word offset = EXTEND16(i_15_0) << 2; - if(vpe_busy) DELAY_SLOT(cia + 4 + offset); + if(vu0_busy()) DELAY_SLOT(cia + 4 + offset); } else if(i_25_21 == 0x08 && i_20_16 == 0x03) /* BC2TL */ { address_word offset = EXTEND16(i_15_0) << 2; - if(vpe_busy) DELAY_SLOT(cia + 4 + offset); + if(vu0_busy()) DELAY_SLOT(cia + 4 + offset); else NULLIFY_NEXT_INSTRUCTION(); } else if((i_25_21 == 0x02 && i_10_1 == 0x000) || /* CFC2 */ - (i_25_21 == 0x06 && i_10_1 == 0x000)) /* CTC2 */ + (i_25_21 == 0x01)) /* QMFC2 */ { int rt = i_20_16; int id = i_15_11; - int to_vu = (i_25_21 == 0x06); /* transfer direction */ address_word vu_cr_addr; /* VU control register address */ + unsigned_4 data; - if(interlock) - while(vpe_busy) - { - vu0_issue(sd); /* advance one clock cycle */ - vpe_status = sim_core_read_aligned_4 (cpu, cia, read_map, VPE0_STAT); - vpe_busy = vpe_status & 0x00000001; - } - - /* compute VU register address */ - vu_cr_addr = VU0_MST + (id * 16); - - /* read or write word */ - if(to_vu) /* CTC2 */ + /* interlock checking */ + if(vu0_busy_in_macro_mode()) /* busy in macro mode */ { - unsigned_4 data = GPR[rt]; - sim_core_write_aligned_4(cpu, cia, write_map, vu_cr_addr, data); + /* interlock bit invalid here */ + if(interlock) + ; /* XXX: warning */ + + /* always check data hazard */ + while(vu0_macro_hazard_check(id)) + vu0_issue(sd); } - else /* CFC2 */ + else if(vu0_busy_in_micro_mode() && interlock) { - unsigned_4 data = sim_core_read_aligned_4(cpu, cia, read_map, vu_cr_addr); - GPR[rt] = EXTEND64(data); + while(vu0_busy_in_micro_mode()) + vu0_issue(sd); } + + /* compute VU register address */ + if(i_25_21 == 0x01) /* QMFC2 */ + vu_cr_addr = VU0_VF00 + (id * 16); + else /* CFC2 */ + vu_cr_addr = VU0_MST + (id * 16); + + /* read or write word */ + data = sim_core_read_aligned_4(cpu, cia, read_map, vu_cr_addr); + GPR[rt] = EXTEND64(data); } - else if((i_25_21 == 0x01) || /* QMFC2 */ - (i_25_21 == 0x05)) /* QMTC2 */ + else if((i_25_21 == 0x06 && i_10_1 == 0x000) || /* CTC2 */ + (i_25_21 == 0x05)) /* QMTC2 */ { int rt = i_20_16; int id = i_15_11; - int to_vu = (i_25_21 == 0x05); /* transfer direction */ address_word vu_cr_addr; /* VU control register address */ + unsigned_4 data; - if(interlock) - while(vpe_busy) - { - vu0_issue(sd); /* advance one clock cycle */ - vpe_status = sim_core_read_aligned_4 (cpu, cia, read_map, VPE0_STAT); - vpe_busy = vpe_status & 0x00000001; - } - - /* compute VU register address */ - vu_cr_addr = VU0_VF00 + (id * 16); - - /* read or write word */ - if(to_vu) /* CTC2 */ + /* interlock checking */ + if(vu0_busy_in_macro_mode()) /* busy in macro mode */ { - unsigned_4 data = GPR[rt]; - sim_core_write_aligned_4(cpu, cia, write_map, vu_cr_addr, data); + /* interlock bit invalid here */ + if(interlock) + ; /* XXX: warning */ + + /* always check data hazard */ + while(vu0_macro_hazard_check(id)) + vu0_issue(sd); } - else /* CFC2 */ + else if(vu0_busy_in_micro_mode()) { - unsigned_4 data = sim_core_read_aligned_4(cpu, cia, read_map, vu_cr_addr); - GPR[rt] = EXTEND64(data); + if(interlock) + { + while(! vu0_micro_interlock_released()) + vu0_issue(sd); + } } + + /* compute VU register address */ + if(i_25_21 == 0x05) /* QMTC2 */ + vu_cr_addr = VU0_VF00 + (id * 16); + else /* CTC2 */ + vu_cr_addr = VU0_MST + (id * 16); + + data = GPR[rt]; + sim_core_write_aligned_4(cpu, cia, write_map, vu_cr_addr, data); + } + else if( 0 /* XXX: ... upper ... */) + { + unsigned_4 vu_upper, vu_lower; + vu_upper = + 0x00000000 | /* bits 31 .. 25 */ + instruction & 0x01ffffff; /* bits 24 .. 0 */ + vu_lower = 0x8000033c; /* NOP */ + + while(vu0_busy_in_micro_mode()) + vu0_issue(sd); + + vu0_macro_issue(vu_upper, vu_lower); + } + else if( 0 /* XXX: ... lower ... */) + { + unsigned_4 vu_upper, vu_lower; + vu_upper = 0x000002ff; /* NOP */ + vu_lower = + 0x10000000 | /* bits 31 .. 25 */ + instruction & 0x01ffffff; /* bits 24 .. 0 */ + + while(vu0_busy_in_micro_mode()) + vu0_issue(sd); + + vu0_macro_issue(vu_upper, vu_lower); } - /* other COP2 instructions */ + /* XXX */ + /* ... other COP2 instructions ... */ else { - SignalException(ReservedInstruction,instruction); + SignalException(ReservedInstruction, instruction); /* NOTREACHED */ } diff --git a/sim/mips/sim-main.h b/sim/mips/sim-main.h index 87a434c5571..f2ebb23fe64 100644 --- a/sim/mips/sim-main.h +++ b/sim/mips/sim-main.h @@ -763,23 +763,26 @@ void signal_exception (SIM_DESC sd, sim_cpu *cpu, address_word cia, int exceptio void cop_lw PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg, unsigned int memword)); void cop_ld PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg, uword64 memword)); -void cop_lq PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg, unsigned128 memword)); unsigned int cop_sw PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg)); uword64 cop_sd PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg)); -unsigned128 cop_sq PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg)); #define COP_LW(coproc_num,coproc_reg,memword) \ cop_lw (SD, CPU, cia, coproc_num, coproc_reg, memword) #define COP_LD(coproc_num,coproc_reg,memword) \ cop_ld (SD, CPU, cia, coproc_num, coproc_reg, memword) -#define COP_LQ(coproc_num,coproc_reg,memword) \ -cop_lq (SD, CPU, cia, coproc_num, coproc_reg, memword) #define COP_SW(coproc_num,coproc_reg) \ cop_sw (SD, CPU, cia, coproc_num, coproc_reg) #define COP_SD(coproc_num,coproc_reg) \ cop_sd (SD, CPU, cia, coproc_num, coproc_reg) + +/* start-sanitize-sky */ +void cop_lq PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg, unsigned128 memword)); +unsigned128 cop_sq PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg)); +#define COP_LQ(coproc_num,coproc_reg,memword) \ +cop_lq (SD, CPU, cia, coproc_num, coproc_reg, memword) #define COP_SQ(coproc_num,coproc_reg) \ cop_sq (SD, CPU, cia, coproc_num, coproc_reg) +/* end-sanitize-sky */ void decode_coproc PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, unsigned int instruction)); #define DecodeCoproc(instruction) \