From: Wilco Dijkstra Date: Wed, 18 Sep 2019 18:11:24 +0000 (+0000) Subject: [ARM] Cleanup multiply patterns X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6f1628c9df05591721192193f6364e316e45c6c1;p=gcc.git [ARM] Cleanup multiply patterns Cleanup the 32-bit multiply patterns. Merge the pre-Armv6 with the Armv6 patterns, remove useless alternatives and order the accumulator operands to prefer MLA Ra, Rb, Rc, Ra whenever feasible. gcc/ * config/arm/arm.md (arm_mulsi3): Remove pattern. (arm_mulsi3_v6): Likewise. (mulsi3addsi_v6): Likewise. (mulsi3subsi): Likewise. (mul): Add new multiply pattern. (mla): Likewise. (mls): Likewise. From-SVN: r275897 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index edf8028925c..2b55a3f4dc7 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,13 @@ +2019-09-18 Wilco Dijkstra + + * config/arm/arm.md (arm_mulsi3): Remove pattern. + (arm_mulsi3_v6): Likewise. + (mulsi3addsi_v6): Likewise. + (mulsi3subsi): Likewise. + (mul): Add new multiply pattern. + (mla): Likewise. + (mls): Likewise. + 2019-09-18 Richard Biener * tree-parloops.c (report_ploop_op): Copy from report_vect_op. diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 6513c2d0203..4ffc7718c7a 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -1595,28 +1595,46 @@ "" ) -;; Use `&' and then `0' to prevent the operands 0 and 1 being the same -(define_insn "*arm_mulsi3" - [(set (match_operand:SI 0 "s_register_operand" "=&r,&r") - (mult:SI (match_operand:SI 2 "s_register_operand" "r,r") - (match_operand:SI 1 "s_register_operand" "%0,r")))] - "TARGET_32BIT && !arm_arch6" +;; Use `&' and then `0' to prevent operands 0 and 2 being the same +(define_insn "*mul" + [(set (match_operand:SI 0 "s_register_operand" "=l,r,&r,&r") + (mult:SI (match_operand:SI 2 "s_register_operand" "l,r,r,r") + (match_operand:SI 1 "s_register_operand" "%0,r,0,r")))] + "TARGET_32BIT" "mul%?\\t%0, %2, %1" [(set_attr "type" "mul") - (set_attr "predicable" "yes")] + (set_attr "predicable" "yes") + (set_attr "arch" "t2,v6,nov6,nov6") + (set_attr "length" "4") + (set_attr "predicable_short_it" "yes,no,*,*")] ) -(define_insn "*arm_mulsi3_v6" - [(set (match_operand:SI 0 "s_register_operand" "=l,l,r") - (mult:SI (match_operand:SI 1 "s_register_operand" "0,l,r") - (match_operand:SI 2 "s_register_operand" "l,0,r")))] - "TARGET_32BIT && arm_arch6" - "mul%?\\t%0, %1, %2" - [(set_attr "type" "mul") +;; MLA and MLS instruction. Use operand 1 for the accumulator to prefer +;; reusing the same register. + +(define_insn "*mla" + [(set (match_operand:SI 0 "s_register_operand" "=r,&r,&r,&r") + (plus:SI + (mult:SI (match_operand:SI 3 "s_register_operand" "r,r,r,r") + (match_operand:SI 2 "s_register_operand" "%r,r,0,r")) + (match_operand:SI 1 "s_register_operand" "r,0,r,r")))] + "TARGET_32BIT" + "mla%?\\t%0, %3, %2, %1" + [(set_attr "type" "mla") (set_attr "predicable" "yes") - (set_attr "arch" "t2,t2,*") - (set_attr "length" "4") - (set_attr "predicable_short_it" "yes,yes,no")] + (set_attr "arch" "v6,nov6,nov6,nov6")] +) + +(define_insn "*mls" + [(set (match_operand:SI 0 "s_register_operand" "=r") + (minus:SI + (match_operand:SI 1 "s_register_operand" "r") + (mult:SI (match_operand:SI 3 "s_register_operand" "r") + (match_operand:SI 2 "s_register_operand" "r"))))] + "TARGET_32BIT && arm_arch_thumb2" + "mls%?\\t%0, %3, %2, %1" + [(set_attr "type" "mla") + (set_attr "predicable" "yes")] ) (define_insn "*mulsi3_compare0" @@ -1673,32 +1691,6 @@ (set_attr "type" "muls")] ) -;; Unnamed templates to match MLA instruction. - -(define_insn "*mulsi3addsi" - [(set (match_operand:SI 0 "s_register_operand" "=&r,&r,&r,&r") - (plus:SI - (mult:SI (match_operand:SI 2 "s_register_operand" "r,r,r,r") - (match_operand:SI 1 "s_register_operand" "%0,r,0,r")) - (match_operand:SI 3 "s_register_operand" "r,r,0,0")))] - "TARGET_32BIT && !arm_arch6" - "mla%?\\t%0, %2, %1, %3" - [(set_attr "type" "mla") - (set_attr "predicable" "yes")] -) - -(define_insn "*mulsi3addsi_v6" - [(set (match_operand:SI 0 "s_register_operand" "=r") - (plus:SI - (mult:SI (match_operand:SI 2 "s_register_operand" "r") - (match_operand:SI 1 "s_register_operand" "r")) - (match_operand:SI 3 "s_register_operand" "r")))] - "TARGET_32BIT && arm_arch6" - "mla%?\\t%0, %2, %1, %3" - [(set_attr "type" "mla") - (set_attr "predicable" "yes")] -) - (define_insn "*mulsi3addsi_compare0" [(set (reg:CC_NOOV CC_REGNUM) (compare:CC_NOOV @@ -1763,18 +1755,6 @@ (set_attr "type" "mlas")] ) -(define_insn "*mulsi3subsi" - [(set (match_operand:SI 0 "s_register_operand" "=r") - (minus:SI - (match_operand:SI 3 "s_register_operand" "r") - (mult:SI (match_operand:SI 2 "s_register_operand" "r") - (match_operand:SI 1 "s_register_operand" "r"))))] - "TARGET_32BIT && arm_arch_thumb2" - "mls%?\\t%0, %2, %1, %3" - [(set_attr "type" "mla") - (set_attr "predicable" "yes")] -) - (define_expand "maddsidi4" [(set (match_operand:DI 0 "s_register_operand") (plus:DI