From: Dmitry Selyutin <ghostmansd@gmail.com>
Date: Sat, 17 Sep 2022 13:54:01 +0000 (+0300)
Subject: power_insn: support vec2/vec3/vec4
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6f1ee0f326b14026f3ff31fe3f22e3a29e56ebc8;p=openpower-isa.git

power_insn: support vec2/vec3/vec4
---

diff --git a/src/openpower/decoder/power_insn.py b/src/openpower/decoder/power_insn.py
index fcb673e7..40b32e6d 100644
--- a/src/openpower/decoder/power_insn.py
+++ b/src/openpower/decoder/power_insn.py
@@ -1280,7 +1280,12 @@ class BaseRM(_Mapping):
 
     @property
     def specifiers(self):
-        yield from ()
+        if self.subvl == 1:
+            yield "vec2"
+        elif self.subvl == 2:
+            yield "vec3"
+        elif self.subvl == 3:
+            yield "vec4"
 
     def disassemble(self, verbosity=Verbosity.NORMAL):
         if verbosity >= Verbosity.VERBOSE: