From: Bin Cheng <bin.cheng@arm.com>
Date: Fri, 5 Sep 2014 03:33:38 +0000 (+0000)
Subject: arm.md (arm_movqi_insn): Use Uh instead of m constraint.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6f22122491661053297b7fbc1a13d162d977e3bd;p=gcc.git

arm.md (arm_movqi_insn): Use Uh instead of m constraint.


	* config/arm/arm.md (arm_movqi_insn): Use Uh instead of m constraint.

From-SVN: r214936
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 27169c22119..1e7d9e15dbd 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,7 @@
+2014-09-05  Bin Cheng  <bin.cheng@arm.com>
+
+	* config/arm/arm.md (arm_movqi_insn): Use Uh instead of m constraint.
+
 2014-09-05  Bin Cheng  <bin.cheng@arm.com>
 
 	* config/arm/arm.c (output_move_neon): Handle REG explicitly.
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index cd9ab6cbb27..f394855d60e 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -6425,7 +6425,7 @@
 
 (define_insn "*arm_movqi_insn"
   [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,l,r,l,Uu,r,m")
-	(match_operand:QI 1 "general_operand" "rk,rk,I,Py,K,Uu,l,m,r"))]
+	(match_operand:QI 1 "general_operand" "rk,rk,I,Py,K,Uu,l,Uh,r"))]
   "TARGET_32BIT
    && (   register_operand (operands[0], QImode)
        || register_operand (operands[1], QImode))"