From: Uros Bizjak Date: Mon, 10 Sep 2018 19:13:49 +0000 (+0200) Subject: i386.md (xf2): Rename from *xf2_i387. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6f2dde9cf68ab68eeadad7cf2772bbba01c997ff;p=gcc.git i386.md (xf2): Rename from *xf2_i387. * config/i386/i386.md (xf2): Rename from *xf2_i387. (*_extendxf2_i387): Remove insn pattern. (mode2): New expander. (sincos_extendxf3_i387): Remove insn pattern. (sincos -> sin, cos splitters): Remove splitter patterns. (sincos3): Change operand 2 predicate to general_operand. Extend operand 2 to XFmode and generate sincosxf3 insn. (fptanxf4_i387): Change mode of operands 0 and 3 to SFmode. Change operand 3 predicate to const1_operand. (fptan_extendxf4_i387): Remove insn pattern. (tanxf2): Update operands in the call to fptanxf4_i387. (tan2): Change operand 1 predicate to general_operand. Extend operand 1 to XFmode and generate tanxf3 insn. (atan2xf3): Rename from *fpatanxf3_i387. (fpatan_extendxf3_i387): Remove insn pattern. (atan2xf3): Remove expander. (atan22): Change operand 1 predicate to general_operand. Extend operand 1 to XFmode and generate atanxf3 insn. From-SVN: r264195 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 54c17b76039..80991766b65 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,26 @@ +2018-09-10 Uros Bizjak + + * config/i386/i386.md (xf2): Rename from *xf2_i387. + (*_extendxf2_i387): Remove insn pattern. + (mode2): New expander. + (sincos_extendxf3_i387): Remove insn pattern. + (sincos -> sin, cos splitters): Remove splitter patterns. + (sincos3): Change operand 2 predicate to general_operand. + Extend operand 2 to XFmode and generate sincosxf3 insn. + (fptanxf4_i387): Change mode of operands 0 and 3 to SFmode. + Change operand 3 predicate to const1_operand. + (fptan_extendxf4_i387): Remove insn pattern. + (tanxf2): Update operands in the call to fptanxf4_i387. + (tan2): Change operand 1 predicate to general_operand. + Extend operand 1 to XFmode and generate tanxf3 insn. + (atan2xf3): Rename from *fpatanxf3_i387. + (fpatan_extendxf3_i387): Remove insn pattern. + (atan2xf3): Remove expander. + (atan22): Change operand 1 predicate to general_operand. + Extend operand 1 to XFmode and generate atanxf3 insn. + 2018-09-10 Uros Bizjak * config/i386/i386.md (x87/SSE constant load splitter): Use diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index c2fa68551ec..4a0a508e2b5 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -15375,7 +15375,7 @@ [(UNSPEC_SIN "sin") (UNSPEC_COS "cos")]) -(define_insn "*xf2_i387" +(define_insn "xf2" [(set (match_operand:XF 0 "register_operand" "=f") (unspec:XF [(match_operand:XF 1 "register_operand" "0")] SINCOS))] @@ -15386,25 +15386,23 @@ (set_attr "znver1_decode" "vector") (set_attr "mode" "XF")]) -(define_insn "*_extendxf2_i387" - [(set (match_operand:XF 0 "register_operand" "=f") - (unspec:XF [(float_extend:XF - (match_operand:MODEF 1 "register_operand" "0"))] - SINCOS))] +(define_expand "2" + [(set (match_operand:MODEF 0 "register_operand") + (unspec:MODEF [(match_operand:MODEF 1 "general_operand")] + SINCOS))] "TARGET_USE_FANCY_MATH_387 && (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387) && flag_unsafe_math_optimizations" - "f" - [(set_attr "type" "fpspc") - (set_attr "znver1_decode" "vector") - (set_attr "mode" "XF")]) +{ + rtx op0 = gen_reg_rtx (XFmode); + rtx op1 = gen_reg_rtx (XFmode); -;; When sincos pattern is defined, sin and cos builtin functions will be -;; expanded to sincos pattern with one of its outputs left unused. -;; CSE pass will figure out if two sincos patterns can be combined, -;; otherwise sincos pattern will be split back to sin or cos pattern, -;; depending on the unused output. + emit_insn (gen_extendxf2 (op1, operands[1])); + emit_insn (gen_xf2 (op0, op1)); + emit_insn (gen_truncxf2 (operands[0], op0)); + DONE; +}) (define_insn "sincosxf3" [(set (match_operand:XF 0 "register_operand" "=f") @@ -15419,70 +15417,10 @@ (set_attr "znver1_decode" "vector") (set_attr "mode" "XF")]) -(define_split - [(set (match_operand:XF 0 "register_operand") - (unspec:XF [(match_operand:XF 2 "register_operand")] - UNSPEC_SINCOS_COS)) - (set (match_operand:XF 1 "register_operand") - (unspec:XF [(match_dup 2)] UNSPEC_SINCOS_SIN))] - "find_regno_note (insn, REG_UNUSED, REGNO (operands[0])) - && can_create_pseudo_p ()" - [(set (match_dup 1) (unspec:XF [(match_dup 2)] UNSPEC_SIN))]) - -(define_split - [(set (match_operand:XF 0 "register_operand") - (unspec:XF [(match_operand:XF 2 "register_operand")] - UNSPEC_SINCOS_COS)) - (set (match_operand:XF 1 "register_operand") - (unspec:XF [(match_dup 2)] UNSPEC_SINCOS_SIN))] - "find_regno_note (insn, REG_UNUSED, REGNO (operands[1])) - && can_create_pseudo_p ()" - [(set (match_dup 0) (unspec:XF [(match_dup 2)] UNSPEC_COS))]) - -(define_insn "sincos_extendxf3_i387" - [(set (match_operand:XF 0 "register_operand" "=f") - (unspec:XF [(float_extend:XF - (match_operand:MODEF 2 "register_operand" "0"))] - UNSPEC_SINCOS_COS)) - (set (match_operand:XF 1 "register_operand" "=u") - (unspec:XF [(float_extend:XF (match_dup 2))] UNSPEC_SINCOS_SIN))] - "TARGET_USE_FANCY_MATH_387 - && (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH) - || TARGET_MIX_SSE_I387) - && flag_unsafe_math_optimizations" - "fsincos" - [(set_attr "type" "fpspc") - (set_attr "znver1_decode" "vector") - (set_attr "mode" "XF")]) - -(define_split - [(set (match_operand:XF 0 "register_operand") - (unspec:XF [(float_extend:XF - (match_operand:MODEF 2 "register_operand"))] - UNSPEC_SINCOS_COS)) - (set (match_operand:XF 1 "register_operand") - (unspec:XF [(float_extend:XF (match_dup 2))] UNSPEC_SINCOS_SIN))] - "find_regno_note (insn, REG_UNUSED, REGNO (operands[0])) - && can_create_pseudo_p ()" - [(set (match_dup 1) - (unspec:XF [(float_extend:XF (match_dup 2))] UNSPEC_SIN))]) - -(define_split - [(set (match_operand:XF 0 "register_operand") - (unspec:XF [(float_extend:XF - (match_operand:MODEF 2 "register_operand"))] - UNSPEC_SINCOS_COS)) - (set (match_operand:XF 1 "register_operand") - (unspec:XF [(float_extend:XF (match_dup 2))] UNSPEC_SINCOS_SIN))] - "find_regno_note (insn, REG_UNUSED, REGNO (operands[1])) - && can_create_pseudo_p ()" - [(set (match_dup 0) - (unspec:XF [(float_extend:XF (match_dup 2))] UNSPEC_COS))]) - (define_expand "sincos3" [(use (match_operand:MODEF 0 "register_operand")) (use (match_operand:MODEF 1 "register_operand")) - (use (match_operand:MODEF 2 "register_operand"))] + (use (match_operand:MODEF 2 "general_operand"))] "TARGET_USE_FANCY_MATH_387 && (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387) @@ -15490,39 +15428,23 @@ { rtx op0 = gen_reg_rtx (XFmode); rtx op1 = gen_reg_rtx (XFmode); + rtx op2 = gen_reg_rtx (XFmode); - emit_insn (gen_sincos_extendxf3_i387 (op0, op1, operands[2])); + emit_insn (gen_extendxf2 (op2, operands[2])); + emit_insn (gen_sincosxf3 (op0, op1, op2)); emit_insn (gen_truncxf2 (operands[0], op0)); emit_insn (gen_truncxf2 (operands[1], op1)); DONE; }) (define_insn "fptanxf4_i387" - [(set (match_operand:XF 0 "register_operand" "=f") - (match_operand:XF 3 "const_double_operand" "F")) + [(set (match_operand:SF 0 "register_operand" "=f") + (match_operand:SF 3 "const1_operand")) (set (match_operand:XF 1 "register_operand" "=u") (unspec:XF [(match_operand:XF 2 "register_operand" "0")] UNSPEC_TAN))] "TARGET_USE_FANCY_MATH_387 - && flag_unsafe_math_optimizations - && standard_80387_constant_p (operands[3]) == 2" - "fptan" - [(set_attr "type" "fpspc") - (set_attr "znver1_decode" "vector") - (set_attr "mode" "XF")]) - -(define_insn "fptan_extendxf4_i387" - [(set (match_operand:MODEF 0 "register_operand" "=f") - (match_operand:MODEF 3 "const_double_operand" "F")) - (set (match_operand:XF 1 "register_operand" "=u") - (unspec:XF [(float_extend:XF - (match_operand:MODEF 2 "register_operand" "0"))] - UNSPEC_TAN))] - "TARGET_USE_FANCY_MATH_387 - && (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH) - || TARGET_MIX_SSE_I387) - && flag_unsafe_math_optimizations - && standard_80387_constant_p (operands[3]) == 2" + && flag_unsafe_math_optimizations" "fptan" [(set_attr "type" "fpspc") (set_attr "znver1_decode" "vector") @@ -15534,33 +15456,30 @@ "TARGET_USE_FANCY_MATH_387 && flag_unsafe_math_optimizations" { - rtx one = gen_reg_rtx (XFmode); - rtx op2 = CONST1_RTX (XFmode); /* fld1 */ - - emit_insn (gen_fptanxf4_i387 (one, operands[0], operands[1], op2)); + rtx one = gen_reg_rtx (SFmode); + emit_insn (gen_fptanxf4_i387 (one, operands[0], operands[1], + CONST1_RTX (SFmode))); DONE; }) (define_expand "tan2" [(use (match_operand:MODEF 0 "register_operand")) - (use (match_operand:MODEF 1 "register_operand"))] + (use (match_operand:MODEF 1 "general_operand"))] "TARGET_USE_FANCY_MATH_387 && (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387) && flag_unsafe_math_optimizations" { rtx op0 = gen_reg_rtx (XFmode); + rtx op1 = gen_reg_rtx (XFmode); - rtx one = gen_reg_rtx (mode); - rtx op2 = CONST1_RTX (mode); /* fld1 */ - - emit_insn (gen_fptan_extendxf4_i387 (one, op0, - operands[1], op2)); + emit_insn (gen_extendxf2 (op1, operands[1])); + emit_insn (gen_tanxf2 (op0, op1)); emit_insn (gen_truncxf2 (operands[0], op0)); DONE; }) -(define_insn "*fpatanxf3_i387" +(define_insn "atan2xf3" [(set (match_operand:XF 0 "register_operand" "=f") (unspec:XF [(match_operand:XF 1 "register_operand" "0") (match_operand:XF 2 "register_operand" "u")] @@ -15573,44 +15492,23 @@ (set_attr "znver1_decode" "vector") (set_attr "mode" "XF")]) -(define_insn "fpatan_extendxf3_i387" - [(set (match_operand:XF 0 "register_operand" "=f") - (unspec:XF [(float_extend:XF - (match_operand:MODEF 1 "register_operand" "0")) - (float_extend:XF - (match_operand:MODEF 2 "register_operand" "u"))] - UNSPEC_FPATAN)) - (clobber (match_scratch:XF 3 "=2"))] - "TARGET_USE_FANCY_MATH_387 - && (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH) - || TARGET_MIX_SSE_I387) - && flag_unsafe_math_optimizations" - "fpatan" - [(set_attr "type" "fpspc") - (set_attr "znver1_decode" "vector") - (set_attr "mode" "XF")]) - -(define_expand "atan2xf3" - [(parallel [(set (match_operand:XF 0 "register_operand") - (unspec:XF [(match_operand:XF 2 "register_operand") - (match_operand:XF 1 "register_operand")] - UNSPEC_FPATAN)) - (clobber (match_scratch:XF 3))])] - "TARGET_USE_FANCY_MATH_387 - && flag_unsafe_math_optimizations") - (define_expand "atan23" [(use (match_operand:MODEF 0 "register_operand")) - (use (match_operand:MODEF 1 "register_operand")) - (use (match_operand:MODEF 2 "register_operand"))] + (use (match_operand:MODEF 1 "general_operand")) + (use (match_operand:MODEF 2 "general_operand"))] "TARGET_USE_FANCY_MATH_387 && (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387) && flag_unsafe_math_optimizations" { rtx op0 = gen_reg_rtx (XFmode); + rtx op1 = gen_reg_rtx (XFmode); + rtx op2 = gen_reg_rtx (XFmode); - emit_insn (gen_fpatan_extendxf3_i387 (op0, operands[2], operands[1])); + emit_insn (gen_extendxf2 (op2, operands[2])); + emit_insn (gen_extendxf2 (op1, operands[1])); + + emit_insn (gen_atan2xf3 (op0, op2, op1)); emit_insn (gen_truncxf2 (operands[0], op0)); DONE; }) @@ -15623,25 +15521,21 @@ (clobber (match_scratch:XF 3))])] "TARGET_USE_FANCY_MATH_387 && flag_unsafe_math_optimizations" -{ - operands[2] = gen_reg_rtx (XFmode); - emit_move_insn (operands[2], CONST1_RTX (XFmode)); /* fld1 */ -}) + "operands[2] = force_reg (XFmode, CONST1_RTX (XFmode));") (define_expand "atan2" [(use (match_operand:MODEF 0 "register_operand")) - (use (match_operand:MODEF 1 "register_operand"))] + (use (match_operand:MODEF 1 "general_operand"))] "TARGET_USE_FANCY_MATH_387 && (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387) && flag_unsafe_math_optimizations" { rtx op0 = gen_reg_rtx (XFmode); + rtx op1 = gen_reg_rtx (XFmode); - rtx op2 = gen_reg_rtx (mode); - emit_move_insn (op2, CONST1_RTX (mode)); /* fld1 */ - - emit_insn (gen_fpatan_extendxf3_i387 (op0, op2, operands[1])); + emit_insn (gen_extendxf2 (op1, operands[1])); + emit_insn (gen_atanxf2 (op0, op1)); emit_insn (gen_truncxf2 (operands[0], op0)); DONE; }) @@ -15664,7 +15558,7 @@ for (i = 2; i < 6; i++) operands[i] = gen_reg_rtx (XFmode); - emit_move_insn (operands[3], CONST1_RTX (XFmode)); /* fld1 */ + operands[3] = force_reg (XFmode, CONST1_RTX (XFmode)); }) (define_expand "asin2" @@ -15702,7 +15596,7 @@ for (i = 2; i < 6; i++) operands[i] = gen_reg_rtx (XFmode); - emit_move_insn (operands[3], CONST1_RTX (XFmode)); /* fld1 */ + operands[3] = force_reg (XFmode, CONST1_RTX (XFmode)); }) (define_expand "acos2"