From: lkcl <lkcl@web>
Date: Thu, 7 Apr 2022 14:59:27 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2862
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6f32dc153fb1aea5199b83d7164982006a10b0ec;p=libreriscv.git

---

diff --git a/openpower/sv/branches.mdwn b/openpower/sv/branches.mdwn
index f3802e1d9..8fe3f69d2 100644
--- a/openpower/sv/branches.mdwn
+++ b/openpower/sv/branches.mdwn
@@ -192,6 +192,7 @@ Brief description of fields:
   VL is truncated to *exclude* the current element, otherwise it is
   included. SVSTATE.MVL is not altered: only VL.
 * **LRu**: Link Register Update, used in conjunction with LK=1.
+  When LRu=1,LK=0, Link Register is updated unconditionally.
   When LRu=1,LK=1, Link Register will
   only be updated if the Branch Condition succeeds.
   When LRu=0,LK=1, Link Register will only be updated if
@@ -545,7 +546,7 @@ if ctr_ok & cond_ok then
   if AA then NIA <-iea EXTS(BD || 0b00)
   else       NIA <-iea CIA + EXTS(BD || 0b00)
   lr_ok <- ¬lr_ok
-if LK & lr_ok then LR <-iea CIA + 4
+if (LK & lr_ok) | (¬LK & lr_ok) then LR <-iea CIA + 4
 ```
 
 Below is the pseudocode for SVP64 Branches, which is a little less
@@ -605,7 +606,7 @@ if cond_ok then
     if AA then NIA <-iea EXTS(BD || 0b00)
     else       NIA <-iea CIA + EXTS(BD || 0b00)
     lr_ok <- ¬lr_ok
-if LK & lr_ok then LR <-iea CIA + 4
+if (LK & lr_ok) | (¬LK & lr_ok) then LR <-iea CIA + 4
 ```
 
 Pseudocode for Vertical-First Mode:
@@ -729,7 +730,7 @@ for i in 0 to VL-1:
     if ctr_ok & cond_ok then
        NIA <-iea LR[0:61] || 0b00
        lr_ok = ¬lr_ok
-    if LK & lr_ok then LR <-iea CIA + 4
+    if (LK & lr_ok) | (¬LK & lr_ok) then LR <-iea CIA + 4
 ```
 
 The reason why should be clear from this being a Vector loop: