From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 25 Jun 2019 16:33:11 +0000 (-0700)
Subject: Merge remote-tracking branch 'origin/master' into xaig
X-Git-Tag: working-ls180~1237^2~39
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6f36ec8ecf147f8d669f35dd616714af971db6f4;p=yosys.git

Merge remote-tracking branch 'origin/master' into xaig
---

6f36ec8ecf147f8d669f35dd616714af971db6f4
diff --cc CHANGELOG
index 0636e6bad,8c88a7db8..f0154a81e
--- a/CHANGELOG
+++ b/CHANGELOG
@@@ -21,11 -20,8 +21,12 @@@ Yosys 0.8 .. Yosys 0.8-de
      - Added "muxcover -mux{4,8,16}=<cost>"
      - Added "muxcover -dmux=<cost>"
      - Added "muxcover -nopartial"
+     - Added "muxpack" pass
 -    - "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx"
 +    - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
 +    - Added "synth_xilinx -abc9" (experimental)
 +    - Added "synth_ice40 -abc9" (experimental)
 +    - Added "synth -abc9" (experimental)
 +    - "synth_xilinx" to now infer hard shift registers (-nosrl to disable)
      - Fixed sign extension of unsized constants with 'bx and 'bz MSB
  
  
diff --cc techlibs/xilinx/cells_sim.v
index 8261286af,50d588a9e..67b221c95
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@@ -281,7 -278,23 +281,24 @@@ module FDPE_1 (output reg Q, input C, C
    always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
  endmodule
  
+ module RAM32X1D (
+   output DPO, SPO,
+   input  D, WCLK, WE,
+   input  A0, A1, A2, A3, A4,
+   input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4,
+ );
+   parameter INIT = 32'h0;
+   parameter IS_WCLK_INVERTED = 1'b0;
+   wire [4:0] a = {A4, A3, A2, A1, A0};
+   wire [4:0] dpra = {DPRA4, DPRA3, DPRA2, DPRA1, DPRA0};
+   reg [31:0] mem = INIT;
+   assign SPO = mem[a];
+   assign DPO = mem[dpra];
+   wire clk = WCLK ^ IS_WCLK_INVERTED;
+   always @(posedge clk) if (WE) mem[a] <= D;
+ endmodule
+ 
 +(* abc_box_id = 4, abc_scc_break="D" *)
  module RAM64X1D (
    output DPO, SPO,
    input  D, WCLK, WE,