From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 5 Apr 2020 11:37:18 +0000 (+0100)
Subject: update submodule
X-Git-Tag: div_pipeline~1498
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6f3a9e20445cb9e78f59d3f0943f152b9981562a;p=soc.git

update submodule
---

diff --git a/libreriscv b/libreriscv
index c932acee..210b57c1 160000
--- a/libreriscv
+++ b/libreriscv
@@ -1 +1 @@
-Subproject commit c932acee1edf6c376a3225f937d243c8a2bf712b
+Subproject commit 210b57c1f0ebe644c132147f67e543332fc20eeb
diff --git a/src/soc/decoder/pseudo/pywriter.py b/src/soc/decoder/pseudo/pywriter.py
index 40d10e8c..113b37eb 100644
--- a/src/soc/decoder/pseudo/pywriter.py
+++ b/src/soc/decoder/pseudo/pywriter.py
@@ -72,8 +72,9 @@ class PyISAWriter(ISA):
 
 if __name__ == '__main__':
     isa = PyISAWriter()
-    isa.write_pysource('branch')
+    isa.write_pysource('fixedtrap')
     exit(0)
+    isa.write_pysource('branch')
     isa.write_pysource('fixedlogical')
     isa.write_pysource('fixedstore')
     isa.write_pysource('fixedload')