From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 30 Sep 2020 21:33:25 +0000 (+0100)
Subject: add I2C into ls180
X-Git-Tag: 24jan2021_ls180~265
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6f3e74eafa7694b43f5fc937f643b0ae081b9994;p=soc.git

add I2C into ls180
---

diff --git a/src/soc/litex/florent/libresoc/ls180.py b/src/soc/litex/florent/libresoc/ls180.py
index 5331cd7f..6e122c66 100644
--- a/src/soc/litex/florent/libresoc/ls180.py
+++ b/src/soc/litex/florent/libresoc/ls180.py
@@ -123,7 +123,7 @@ _io.append(make_uart("uart", 0))
 _io.append(make_uart("uart", 1))
 
 # not connected - eurgh have to adjust this to match the total pincount.
-num_nc = 42
+num_nc = 40
 nc = ' '.join("NC%d" % i for i in range(num_nc))
 _io.append(("nc", 0, Pins(nc), IOStandard("LVCMOS33")))
 
diff --git a/src/soc/litex/florent/ls180soc.py b/src/soc/litex/florent/ls180soc.py
index fd6c84b9..ecb10bcc 100755
--- a/src/soc/litex/florent/ls180soc.py
+++ b/src/soc/litex/florent/ls180soc.py
@@ -47,7 +47,7 @@ SoCCSRHandler.supported_address_width.append(12)
 # GPIO Tristate -------------------------------------------------------
 # doesn't work properly.
 #from litex.soc.cores.gpio import GPIOTristate
-from litex.soc.interconnect.csr import CSRStorage, CSRStatus
+from litex.soc.interconnect.csr import CSRStorage, CSRStatus, CSRField
 from migen.genlib.cdc import MultiReg
 
 # Imports
@@ -471,10 +471,9 @@ class LibreSoCSim(SoCCore):
             setattr(self.submodules, name, PWM(platform.request("pwm", i)))
             self.add_csr(name)
 
-        if False: # TODO: convert to _i _o _oe
-            # I2C Master
-            self.submodules.i2c = I2CMaster(platform.request("i2c"))
-            self.add_csr("i2c")
+        # I2C Master
+        self.submodules.i2c = I2CMaster(platform.request("i2c"))
+        self.add_csr("i2c")
 
         # SDCard -----------------------------------------------------