From: Michael Nolan <mtnolan2640@gmail.com>
Date: Fri, 8 May 2020 17:32:35 +0000 (-0400)
Subject: Add extra bits (carry, overflow, etc) to input and output structs
X-Git-Tag: div_pipeline~1340
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6f527ce9190c29197232f4a633471e390642f4bb;p=soc.git

Add extra bits (carry, overflow, etc) to input and output structs
---

diff --git a/src/soc/alu/input_stage.py b/src/soc/alu/input_stage.py
index 950f5ba4..f7c38673 100644
--- a/src/soc/alu/input_stage.py
+++ b/src/soc/alu/input_stage.py
@@ -1,7 +1,7 @@
 from nmigen import (Module, Signal, Cat, Const, Mux, Repl, signed,
                     unsigned)
 from nmutil.pipemodbase import PipeModBase
-from soc.alu.pipe_data import ALUInitialData
+from soc.alu.pipe_data import ALUInputData
 
 
 class ALUInputStage(PipeModBase):
@@ -9,10 +9,10 @@ class ALUInputStage(PipeModBase):
         super().__init__(pspec, "input")
 
     def ispec(self):
-        return ALUInitialData(self.pspec)
+        return ALUInputData(self.pspec)
 
     def ospec(self):
-        return ALUInitialData(self.pspec)
+        return ALUInputData(self.pspec)
 
     def elaborate(self, platform):
         m = Module()
diff --git a/src/soc/alu/main_stage.py b/src/soc/alu/main_stage.py
index 941f567c..ee823451 100644
--- a/src/soc/alu/main_stage.py
+++ b/src/soc/alu/main_stage.py
@@ -1,6 +1,6 @@
 from nmigen import (Module, Signal)
 from nmutil.pipemodbase import PipeModBase
-from soc.alu.pipe_data import ALUInitialData, ALUOutputData
+from soc.alu.pipe_data import ALUInputData, ALUOutputData
 from ieee754.part.partsig import PartitionedSignal
 from soc.decoder.power_enums import InternalOp
 
@@ -10,7 +10,7 @@ class ALUMainStage(PipeModBase):
         super().__init__(pspec, "main")
 
     def ispec(self):
-        return ALUInitialData(self.pspec)
+        return ALUInputData(self.pspec)
 
     def ospec(self):
         return ALUOutputData(self.pspec)
@@ -25,7 +25,7 @@ class ALUMainStage(PipeModBase):
 
         with m.Switch(self.i.ctx.op.insn_type):
             with m.Case(InternalOp.OP_ADD):
-                comb += self.o.o.eq(add_output)
+                comb += self.o.o.eq(add_output[0:64])
 
         comb += self.o.ctx.eq(self.i.ctx)
 
diff --git a/src/soc/alu/pipe_data.py b/src/soc/alu/pipe_data.py
index 9db5c9bc..1601bcb3 100644
--- a/src/soc/alu/pipe_data.py
+++ b/src/soc/alu/pipe_data.py
@@ -18,34 +18,56 @@ class IntegerData:
         return [self.op.eq(i.op), self.ctx.eq(i.ctx)]
 
 
-class ALUInitialData(IntegerData):
+class ALUInputData(IntegerData):
     def __init__(self, pspec):
         super().__init__(pspec)
         self.a = Signal(64, reset_less=True)
         self.b = Signal(64, reset_less=True)
+        self.so = Signal(reset_less=True)
+        self.carry_in = Signal(reset_less=True)
 
     def __iter__(self):
         yield from super().__iter__()
         yield self.a
         yield self.b
+        yield self.carry_in
+        yield self.so
 
     def eq(self, i):
         lst = super().eq(i)
-        return lst + [self.a.eq(i.a), self.b.eq(i.b)]
+        return lst + [self.a.eq(i.a), self.b.eq(i.b),
+                      self.carry_in.eq(i.carry_in),
+                      self.so.eq(i.so)]
 
 
 class ALUOutputData(IntegerData):
     def __init__(self, pspec):
         super().__init__(pspec)
         self.o = Signal(64, reset_less=True)
+        self.carry_out = Signal(reset_less=True)
+        self.carry_out32 = Signal(reset_less=True)
+        self.cr0 = Signal(4, reset_less=True)
+        self.ov = Signal(reset_less=True)
+        self.ov32 = Signal(reset_less=True)
+        self.so = Signal(reset_less=True)
 
     def __iter__(self):
         yield from super().__iter__()
         yield self.o
+        yield self.carry_out
+        yield self.carry_out32
+        yield self.cr0
+        yield self.ov
+        yield self.ov32
+        yield self.so
 
     def eq(self, i):
         lst = super().eq(i)
-        return lst + [self.o.eq(i.o)]
+        return lst + [self.o.eq(i.o),
+                      self.carry_out.eq(i.carry_out),
+                      self.carry_out32.eq(i.carry_out32),
+                      self.cr0.eq(i.cr0), self.ov.eq(i.ov),
+                      self.ov32.eq(i.ov32), self.so.eq(i.so)]
 
 class IntPipeSpec:
     def __init__(self, id_wid=2, op_wid=1):