From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 18 Apr 2021 10:27:10 +0000 (+0000)
Subject: update libresoc.v, c4m-jtag fsm was renamed
X-Git-Tag: LS180_RC3~114
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6f52e3ebcaba3b5aca88d39c2a498aed1b46dbfd;p=soclayout.git

update libresoc.v, c4m-jtag fsm was renamed
---

diff --git a/experiments9/non_generated/litex_ls180.v b/experiments9/non_generated/litex_ls180.v
index be1906f..fffddcc 100644
--- a/experiments9/non_generated/litex_ls180.v
+++ b/experiments9/non_generated/litex_ls180.v
@@ -1,9 +1,7 @@
 //--------------------------------------------------------------------------------
-// Auto-generated by Migen (7bc4eb1) & LiteX (35929c0f) on 2021-04-09 00:25:38
+// Auto-generated by Migen (7bc4eb1) & LiteX (35929c0f) on 2021-04-17 09:05:29
 //--------------------------------------------------------------------------------
 module ls180(
-	input wire uart_tx,
-	input wire uart_rx,
 	output wire i2c_scl,
 	input wire i2c_sda_i,
 	output wire i2c_sda_o,
@@ -15,6 +13,8 @@ module ls180(
 	input wire [15:0] gpio_i,
 	output wire [15:0] gpio_o,
 	output wire [15:0] gpio_oe,
+	input wire uart_tx,
+	input wire uart_rx,
 	input wire eint_0,
 	input wire eint_1,
 	input wire eint_2,
@@ -109,8 +109,6 @@ reg [63:0] libresocsim_libresoc0 = 64'd0;
 wire libresocsim_libresoc1;
 wire libresocsim_libresoc2;
 wire [63:0] libresocsim_libresoc3;
-reg libresocsim_libresoc_constraintmanager_uart_tx = 1'd1;
-reg libresocsim_libresoc_constraintmanager_uart_rx = 1'd0;
 wire libresocsim_libresoc_constraintmanager_i2c_scl;
 wire libresocsim_libresoc_constraintmanager_i2c_sda_i;
 wire libresocsim_libresoc_constraintmanager_i2c_sda_o;
@@ -122,6 +120,8 @@ wire libresocsim_libresoc_constraintmanager_spimaster_miso;
 wire [15:0] libresocsim_libresoc_constraintmanager_gpio_i;
 reg [15:0] libresocsim_libresoc_constraintmanager_gpio_o = 16'd0;
 reg [15:0] libresocsim_libresoc_constraintmanager_gpio_oe = 16'd0;
+reg libresocsim_libresoc_constraintmanager_uart_tx = 1'd1;
+reg libresocsim_libresoc_constraintmanager_uart_rx = 1'd0;
 wire libresocsim_libresoc_constraintmanager_eint_0;
 wire libresocsim_libresoc_constraintmanager_eint_1;
 wire libresocsim_libresoc_constraintmanager_eint_2;