From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Thu, 5 Nov 2015 07:06:33 +0000 (+0800)
Subject: fhdl/verilog: create clock domains in deterministic order
X-Git-Tag: 24jan2021_ls180~2099^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6f5bf0292e2886f00ccf6c09a64a1b198ed33383;p=litex.git

fhdl/verilog: create clock domains in deterministic order
---

diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py
index 72888999..19bba1fa 100644
--- a/migen/fhdl/verilog.py
+++ b/migen/fhdl/verilog.py
@@ -323,7 +323,7 @@ def convert(f, ios=None, name="top",
     if ios is None:
         ios = set()
 
-    for cd_name in list_clock_domains(f):
+    for cd_name in sorted(list_clock_domains(f)):
         try:
             f.clock_domains[cd_name]
         except KeyError: