From: whitequark Date: Sat, 26 Jan 2019 16:25:05 +0000 (+0000) Subject: examples: update for newer API. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6f63b200d07a33806184f6b580bf6fff05dae1f6;p=nmigen.git examples: update for newer API. --- diff --git a/examples/arst.py b/examples/arst.py index 22972f3..405857b 100644 --- a/examples/arst.py +++ b/examples/arst.py @@ -15,7 +15,7 @@ class ClockDivisor: if __name__ == "__main__": - ctr = ClockDivisor(factor=16) - frag = ctr.elaborate(platform=None) - frag.add_domains(ClockDomain("sync", async_reset=True)) - main(frag, ports=[ctr.o]) + ctr = ClockDivisor(factor=16) + m = ctr.elaborate(platform=None) + m.domains += ClockDomain("sync", async_reset=True) + main(m, ports=[ctr.o]) diff --git a/examples/cdc.py b/examples/cdc.py index 80b335e..4f2dfad 100644 --- a/examples/cdc.py +++ b/examples/cdc.py @@ -7,4 +7,4 @@ m = Module() m.submodules += MultiReg(i, o) if __name__ == "__main__": - main(m.lower(platform=None), ports=[i, o]) + main(m, ports=[i, o]) diff --git a/examples/ctr_ce.py b/examples/ctr_ce.py index 6a7a095..ebf1db0 100644 --- a/examples/ctr_ce.py +++ b/examples/ctr_ce.py @@ -15,13 +15,11 @@ class Counter: return CEInserter(self.ce)(m.lower(platform)) -ctr = Counter(width=16) -frag = ctr.elaborate(platform=None) +ctr = Counter(width=16) -# print(rtlil.convert(frag, ports=[ctr.o, ctr.ce])) -print(verilog.convert(frag, ports=[ctr.o, ctr.ce])) +print(verilog.convert(ctr, ports=[ctr.o, ctr.ce])) -with pysim.Simulator(frag, +with pysim.Simulator(ctr, vcd_file=open("ctrl.vcd", "w"), gtkw_file=open("ctrl.gtkw", "w"), traces=[ctr.ce, ctr.v, ctr.o]) as sim: diff --git a/examples/por.py b/examples/por.py index 6c3c40f..28e860c 100644 --- a/examples/por.py +++ b/examples/por.py @@ -16,4 +16,4 @@ m.d.comb += [ ] if __name__ == "__main__": - main(m.lower(platform=None), ports=[cd_por.clk]) + main(m, ports=[cd_por.clk]) diff --git a/examples/tbuf.py b/examples/tbuf.py index 4e19af0..5d3566f 100644 --- a/examples/tbuf.py +++ b/examples/tbuf.py @@ -9,4 +9,4 @@ m = Module() m.submodules += pin_t.get_tristate(pin) if __name__ == "__main__": - main(m.lower(platform=None), ports=[pin, pin_t.oe, pin_t.i, pin_t.o]) + main(m, ports=[pin, pin_t.oe, pin_t.i, pin_t.o])