From: whitequark <whitequark@whitequark.org>
Date: Fri, 7 Feb 2020 02:54:04 +0000 (+0000)
Subject: Merge pull request #1683 from whitequark/write_verilog-memattrs
X-Git-Tag: working-ls180~811
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6f67dd8df52e6640f216661ae929cd3ed29d23cf;p=yosys.git

Merge pull request #1683 from whitequark/write_verilog-memattrs

write_verilog: dump $mem cell attributes
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6f67dd8df52e6640f216661ae929cd3ed29d23cf