From: Ian Romanick Date: Thu, 6 Jun 2019 18:12:14 +0000 (-0700) Subject: intel/vec4: Refactor operand fixing for ffma and flrp X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6f6bc842f6672c596edd9c446ff9a1bd0668de0b;p=mesa.git intel/vec4: Refactor operand fixing for ffma and flrp Reviewed-by: Matt Turner --- diff --git a/src/intel/compiler/brw_vec4.h b/src/intel/compiler/brw_vec4.h index 7b25ed61b62..c8804b90f47 100644 --- a/src/intel/compiler/brw_vec4.h +++ b/src/intel/compiler/brw_vec4.h @@ -242,6 +242,9 @@ public: */ src_reg emit_uniformize(const src_reg &src); + /** Fix all float operands of a 3-source instruction. */ + void fix_float_operands(src_reg op[3]); + src_reg fix_3src_operand(const src_reg &src); src_reg resolve_source_modifiers(const src_reg &src); diff --git a/src/intel/compiler/brw_vec4_nir.cpp b/src/intel/compiler/brw_vec4_nir.cpp index a646496fdcf..be7e7d79979 100644 --- a/src/intel/compiler/brw_vec4_nir.cpp +++ b/src/intel/compiler/brw_vec4_nir.cpp @@ -1130,6 +1130,17 @@ try_immediate_source(const nir_alu_instr *instr, src_reg *op, return idx; } +void +vec4_visitor::fix_float_operands(src_reg op[3]) +{ + bool fixed[3] = { false, false, false }; + + for (unsigned i = 0; i < 3; i++) { + if (!fixed[i]) + op[i] = fix_3src_operand(op[i]); + } +} + void vec4_visitor::nir_emit_alu(nir_alu_instr *instr) { @@ -1916,20 +1927,14 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr) inst = emit(ADD(dst, src_reg(mul_dst), op[2])); inst->saturate = instr->dest.saturate; } else { - op[0] = fix_3src_operand(op[0]); - op[1] = fix_3src_operand(op[1]); - op[2] = fix_3src_operand(op[2]); - + fix_float_operands(op); inst = emit(MAD(dst, op[2], op[1], op[0])); inst->saturate = instr->dest.saturate; } break; case nir_op_flrp: - op[0] = fix_3src_operand(op[0]); - op[1] = fix_3src_operand(op[1]); - op[2] = fix_3src_operand(op[2]); - + fix_float_operands(op); inst = emit(LRP(dst, op[2], op[1], op[0])); inst->saturate = instr->dest.saturate; break;