From: Gabe Black <gabe.black@gmail.com>
Date: Mon, 18 Jan 2021 01:48:07 +0000 (-0800)
Subject: arm: Use the "reg" ABI for gem5 ops.
X-Git-Tag: develop-gem5-snapshot~266
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6f74594cc71786c5a3f8863c4eb6cc713faf325e;p=gem5.git

arm: Use the "reg" ABI for gem5 ops.

The generic PseudoInstABI just calls back into the ISA specific
getArgument function, and that adds a lot of handling for cases that
aren't used and, besides those, basically just boils down to the "reg"
ABI anyway.

Change-Id: I57e738631dbccbf89cba3a6ca62b1f954b39e959
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39316
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
---

diff --git a/src/arch/arm/isa/includes.isa b/src/arch/arm/isa/includes.isa
index 13b47c8e0..6af382af2 100644
--- a/src/arch/arm/isa/includes.isa
+++ b/src/arch/arm/isa/includes.isa
@@ -105,6 +105,7 @@ output exec {{
 #include "arch/arm/htm.hh"
 #include "arch/arm/isa_traits.hh"
 #include "arch/arm/pauth_helpers.hh"
+#include "arch/arm/reg_abi.hh"
 #include "arch/arm/semihosting.hh"
 #include "arch/arm/utility.hh"
 #include "arch/generic/memhelpers.hh"
diff --git a/src/arch/arm/isa/insts/m5ops.isa b/src/arch/arm/isa/insts/m5ops.isa
index 9b3206527..fafb44b6e 100644
--- a/src/arch/arm/isa/insts/m5ops.isa
+++ b/src/arch/arm/isa/insts/m5ops.isa
@@ -38,13 +38,14 @@
 let {{
     gem5OpCode = '''
     uint64_t ret;
-    bool recognized = PseudoInst::pseudoInst<PseudoInstABI>(
-            xc->tcBase(), bits(machInst, 23, 16), ret);
-    if (!recognized)
+    int func = bits(machInst, 23, 16);
+    auto *tc = xc->tcBase();
+    if (!PseudoInst::pseudoInst<%s>(tc, func, ret))
         fault = std::make_shared<UndefinedInstruction>(machInst, true);
     '''
     gem5OpIop = ArmInstObjParams("gem5op", "Gem5Op64", "PredOp",
-                                 { "code": gem5OpCode + 'X0 = ret;',
+                                 { "code": gem5OpCode % "RegABI64" +
+                                   'X0 = ret;',
                                    "predicate_test": predicateTest },
                                  [ "IsNonSpeculative", "IsUnverifiable" ]);
     header_output += BasicDeclare.subst(gem5OpIop)
@@ -52,7 +53,7 @@ let {{
     exec_output += PredOpExecute.subst(gem5OpIop)
 
     gem5OpIop = ArmInstObjParams("gem5op", "Gem5Op", "PredOp",
-                                 { "code": gem5OpCode + \
+                                 { "code": gem5OpCode % "RegABI32" + \
                                    'R0 = bits(ret, 31, 0);\n' + \
                                    'R1 = bits(ret, 63, 32);',
                                    "predicate_test": predicateTest },
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index 5d2ed902d..91c70884e 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -47,6 +47,7 @@
 #include "arch/arm/faults.hh"
 #include "arch/arm/isa.hh"
 #include "arch/arm/pagetable.hh"
+#include "arch/arm/reg_abi.hh"
 #include "arch/arm/self_debug.hh"
 #include "arch/arm/stage2_lookup.hh"
 #include "arch/arm/stage2_mmu.hh"
@@ -146,9 +147,14 @@ TLB::finalizePhysical(const RequestPtr &req,
             [func, mode](ThreadContext *tc, PacketPtr pkt) -> Cycles
             {
                 uint64_t ret;
-                PseudoInst::pseudoInst<PseudoInstABI>(tc, func, ret);
+                if (inAArch64(tc))
+                    PseudoInst::pseudoInst<RegABI64>(tc, func, ret);
+                else
+                    PseudoInst::pseudoInst<RegABI32>(tc, func, ret);
+
                 if (mode == Read)
                     pkt->setLE(ret);
+
                 return Cycles(1);
             }
         );